HV461 Supertex, Inc., HV461 Datasheet - Page 11

• Manufacturer Part Number: HV461
• Description: Ring Generator Controller Ic
• Manufacturer: Supertex, Inc.

Pin Description
Pin
10
12
13
14
15
16
17
18
19
20
11
1
2
3
4
5
6
7
8
9
SYNCMODE
PWMSYNC
DCREF3
ENABLE
CFAULT
TSYNC
PLLFLT
VREF1
VREF2
RESET
FRING
FAULT
ROSC
AVDD
SYNC
AMP0
AMP1
Name
OFF0
OFF1
XTAL
See DCREF1 and DCREF2 (pins 47 & 48).
Outputs a 1.25V nominal reference voltage. Bypass with a 100nF capacitor to ground.
Outputs a 2.50V nominal reference voltage. Bypass with a 100nF capacitor to ground.
Supply for the analog section. 3.0 to 3.6V Must be from the same source as DVDD. Bypass with a 100nF capacitor to ground as close as
possible to the IC.
An RC network connected to this pin determines the SYNC pulse lead time (see SYNC pin 14). t
must still have a connected RC network.
A crystal from this pin to ground provides the frequency reference for the internal sine wave synthesizer. A 19.6608MHz baud rate crystal
provides the 8 most common ring frequencies. The crystal is operated in the series mode. A loading capacitor is not necessary. See also
FREQ0–2 (pins 21–23) and FRING (pin 7).
Ring frequency is normally selected from the 8 built-in frequencies using control inputs FREQ0–2. Other arbitrary frequencies in the range
of 12 to 63Hz may be obtained by applying an external signal to FRING. This external signal sets the ring frequency at a 1:1 ratio. The ring
signal remains a sine wave, with amplitude and offset still controlled via AMPx and OFFx. The ring signal, while frequency locked to the FRING
signal, is not phase–synchronized to it. This allows the ring signal to immediately start at 0º when enabled via ENABLE or AMP ≠ 00. When
unused, this input must be connected to VGD.
Phase locked loop fi lter. An RC network connected to this pin stabilizes the PLL that locks on to the optional external ring frequency signal.
(See FRING, pin 7) The RC network determines the lock time of the PLL. Due to the low frequencies involved, it may take a couple seconds
to lock to the external signal. See the typical application schematic for typical values. When unused, this pin should be left unconnected.
A resistor from this pin to VDD sets the PWM frequency. f
A capacitor from this pin to ground provides a power–on reset interval. It has an internal 10µA pull–up to charge the external reset capacitor.
Alternatively, an external logic–level or open–drain signal may be applied to implement the reset function. During the reset interval when
V
control. Use a low leakage tantalum or ceramic capacitor. t
This pin functions as both an input and an output. It is open–drain with an internal 100µA pull-up. As an output, it provides a short, low-going
pulse at the internal PWM frequency. As an input, it synchronizes internal PWM frequency to the externally applied signal, provided the
external signal is at a higher frequency. The low-going applied sync pulse should be between 25ns and less than the PWM period in duration.
The external source should be open drain. If the PWMSYNC pins of multiple HV461s are tied together, their PWM frequencies will be phase-
locked to the HV461 with the highest free-running frequency. A maximum of 10 HV461s may be tied together. If unused, this pin should be
left unconnected.
A capacitor from this pin to ground sets the integration time of the FAULT detection circuitry. A larger capacitor provides less suseptability to
transient problems, while a smaller capacitor provides quicker response. Values in the range of 1µF to 100µF are appropriate. If the FAULT
output is not used, this pin should be grounded. See also FAULT (pin 15).
With SYNCMODE low, ringer output ceases the instant ENABLE goes low. When high, ringer output ceases at the next ring signal phase
crossing (0º/180º) after ENABLE goes low.
Outputs a pulse indicating sine reference 0º and 180º phase crossing (not to be confused with zero–voltage crossing). The rising edge
precedes phase crossing by a user–adjustable time period (see TSYNC pin 44). Falling edge coincides with sine reference phase crossing.
SYNC is digitally derived, therefore phase shifts caused by the external fi lter capacitor at SINEREF will not be refl ected at the SYNC output.
Indicates abnormal operating conditions of output overcurrent, supply undervoltage (VDD & VGD), or PWM overrange (duty cycle limit – see
VDCL, pin 3). Together, these 3 conditions catch most any problem. When an overcurrent or overrange condition exists for more than 8% of
the time, this output becomes active. It is cleared when the problem occurs less than 2% of the time. Undervoltage conditions immediately
activate the FAULT output. It is active low and open drain to allow wire-ORing. See CFAULT (pin 15) for additional information.
Ringer output enable. Active high. When enabled, the ring signal always starts immediately at 0 degrees. If AMP≠00, SW1 and SW2 are held
off when ENABLE=0 but SW3 and SW4 continue switching. If AMP=00, SW3 and SW4 are held off as well. When disabled, the error amplifi er
is set at unity gain to prevent saturation, reducing turn-on glitches when re-enabled. See SYNCMODE (pin 13) for additional information.
Sets ring DC offset. Offset changes are effected at the next phase crossing (0º/180º) of the ring signal. Except for 00, offsets are set by the
voltages at DCREF1–3. (OFF0 is LSB) Offset = ½ x Gain x (V
Sets ring amplitude. Amplitude changes are effected at the next phase crossing (0º/180º) of the ring signal.
Amplitudes, as a percentage of full scale, are: (AMP0 is LSB) Full scale amplitude = 0.707V
Description
RESET
<1.325V, the ringer output is disabled regardless of the state of the ENABLE input, allowing time for the host controller to assume
(refer to pin confi guration on page 2)
00 = 0V
00 = 0%
01 = DCREF1
01 = 50%
11
PWM
RESET
≈ 12.5GHzΩ / R
DCREFx
= 1.325V · C
- V
REF1
)
10 = DCREF2
10 = 75%
RESET
OSC
(valid for 20-150kHz)
/ 10µA
RMS
LEAD
x Gain
= 0.48RC If SYNC is not utilized, TSYNC
11 = DCREF3
11 = 100%
HV461