RS5C313 RICOH Co.,Ltd., RS5C313 Datasheet - Page 15

• Manufacturer Part Number: RS5C313
• Description: Ultra-compact Real-time Clock Ic
• Manufacturer: RICOH Co.,Ltd.

2. Write Data
Writing data to the real-time clock requires inputting setting data (control bits and address bits) to the SIO pin and
then establishing the write mode by using a control bit R/W in the same manner as in read operation.
• Data bits
2.1 Write Cycle Flow
1. The CE pin is switched from the low level to the high level.
2. Four control bits (with the first bit ignored) and four write address bits are input from the SIO pin. At this time,
3. Four control bits and four bits of data to be written are input in the descending order of their significance. At this
4. When write cycle is continued, control bits and address bits are input at the shift clock pulse 1C and later in the
5. At the end of write operation, control bits R/W, AD, and DT are set equally to 0 (at the falling edge of the fifth
*
*
) Control bits and address bits are described in the previous section on read cycle.
control bits R/W and DT are set equally to 0 while a control bit AD is set to 1 (at the shift clock pulses 1A to 8A
from the SCLK pin).
time, control bits R/W and AD are set equally to 0 while a control bit DT is set to 1 (at the shift clock pulses 1B
to 8B from the SCLK pin).
same manner as at the shift clock pulse 1A.
shift clock pulse and later from the SCLK pin) or the CE pin is switched from the high level to the low level (after
t
) In the above figure, the “
Input to
SIO pin
Output from
SIO pin
(Internal processing)
CEH
CE
SCLK
from the falling edge of the eighth shift clock pulse from the SCLK pin).
*
D3 to D0 : inputs writing data to the counter or the register describing the functions in order of MSB
Reading from shift register
1A
(Hi-z)
*
2A
R/W AD
Control bits
*
” mark indicates arbitrary data; and the diagonally shaded area indicates the high or low level.
to LSB.
3A
4A
DT
Setting of
control bits
5A
A3
Address bits
6A
A2
7A
A1
Writing to
address register
8A
A0
1B
*
2B
R/W AD
Control bits
3B
4B
DT
Setting of
control bits
5B
D3
6B
D2
Data bits
7B
D1
8B
D0
End of write operation
1C
*
(Hi-z)
2C
R/W AD
3C
RS5C313
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