RS5C313 RICOH Co.,Ltd., RS5C313 Datasheet - Page 8

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RS5C313

Manufacturer Part Number
RS5C313
Description
Ultra-compact Real-time Clock Ic
Manufacturer
RICOH Co.,Ltd.
Datasheet

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8
RS5C313
2. Register
2.1 Control Register (at Eh)
2.1-1 (ADJ)
When the ADJ bit is set to 1: (If the WTEN bit is 0, adjustment of second digits is started after the WTEN bit is set to 1.)
1) For second digits ranging from 00 to 29 seconds:
2) For second digits ranging from 30 to 59 seconds:
CTFG
CTFG
D3
12/24
12/24
D2
WTEN
XSTP
D1
BSY
ADJ
D0
Clock/Calendar Counter Busy-state Indication Bit
Clock Counter Enable/Disable Setting Bit
Oscillator Halt Sensing Bit
12/24-hour Time Display System Selection Bit
Interrupt Flag Bit
±30-second Adjustment Bit
(For write operation)
(For read operation)
WTEN
XSTP
CTFG
12/24
ADJ
BSY
0
1
0
1
0
1
0
1
0
1
0
1
Time counts smaller than seconds are reset to set second digits to “00”.
Time counts smaller than seconds are reset to set second digits to “00”
and increment minute digits by 1. After the ADJ bit is set to 1, the BSY
bit is set to 1 for the maximum duration of 122.1µs.
Ordinary operation
Second digit adjustment
Ordinary operation
Second digit carry or adjustment
Disabling of 1-second digit carry for clock counter
Enabling of 1-second digit carry for clock counter
Ordinary oscillation
Oscillator halt sensing
12-hour time display system (separate for mornings and afternoons)
24-hour time display system
INTR=H(Nch Open Drain). Enabling of write operation when the CT3 bit is set to 1.
INTR=L (Nch Open Drain). Enabling of write operation when the CT3 bit is set to 1.
Description
Description
Description
Description
Description
Description

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