HT46R12A Holtek Semiconductor Inc., HT46R12A Datasheet - Page 22

• Manufacturer Part Number: HT46R12A
• Description: Ht46r12a -- A/d Type 8-bit Otp Mcu
• Manufacturer: Holtek Semiconductor Inc.

Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PC, which are
mapped to the data memory of [12H], [14H] and [16H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H
or 16H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be re-
configured dynamically under software control. To func-
tion as an input, the corresponding latch of the control
register must write 1 . The input source also depends
on the control register. If the control register bit is 1 ,
the input will read the pad state. If the control register bit
is 0 , the contents of the latches will move to the inter-
nal bus. The latter is possible in the read-modify-write
instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 17H.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H or
16H) instructions.
Rev. 1.00
Input/Output Ports
22
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there s none. Take note that a
non-pull-high I/O port operating in input mode will cause
a floating state.
The PA3, PA4 and PA7 are pin-shared with PFD, TMR0
and TMR1 pins respectively. And the PC0, PC1, PC2,
PC3 and PC4 are pin-shared with C0VIN1-, C0VIN+,
C0OUT, C1OUT and C1VIN-.
The PA3 is pin-shared with the PFD signal. If the PFD op-
tion is selected, the output signal in output mode of PA3
will be the PFD signal generated by a timer/event counter
overflow signal. The input mode always remain in its orig-
inal functions. Once the PFD option is selected, the PFD
output signal is controlled by the PA3 data register only.
Writing 1 to PA3 data register will enable the PFD out-
put function and writing 0 will force the PA3 to remain at
Note:
0 . The I/O functions of PA3 are shown below.
Mode
PA3
I/O
The PFD frequency is the timer/event counter
overflowfrequencydividedby 2.
(Normal)
Logical
Input
I/P
(Normal)
Logical
Output
O/P
Logical
(PFD)
Input
I/P
HT46R12A
August 3, 2007
(Timer on)
(PFD)
PFD
O/P