HT46R63 Holtek Semiconductor Inc., HT46R63 Datasheet
HT46R63
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HT46R63 Summary of contents
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... RISC architecture microcontroller devices specifically designed for A/D product applications that interface di- rectly to analog signals and which require LCD Inter- face. The mask version HT46C63 is fully pin and functionally compatible with the OTP version HT46R63 device. Rev. 2.30 HT46R63/HT46C63 A/D with LCD Type 8-Bit MCU 8-level stack ...
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... Block Diagram Rev. 2.30 HT46R63/HT46C63 2 March 22, 2006 ...
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... Pin Assignment Rev. 2.30 HT46R63/HT46C63 3 March 22, 2006 ...
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... LCD highest voltage; should be connected to VDD with external resistor. LCD segment signal driving outputs SEG7~SEG10 can be optioned as out- put lines. SEG11~SEG14, SEG15~SEG18 can be optioned as a high sink- ing output lines. LCD common signal driving outputs +6.0V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... HT46R63/HT46C63 March 22, 2006 ...
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... V =0. =0. =0. =0. =0. HT46R63/HT46C63 Ta=25 C Typ. Max. Unit 5 104 136 0. ...
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... 0 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 2.2V~5.5V 0 3.3V~5. Power-up or wake-up from HALT HT46R63/HT46C63 Typ. Max. Unit 100 mA 60 100 0 LSB 0 Ta=25 C Typ. Max. Unit 4000 kHz 8000 ...
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... S11~S8 Note: *11~*0: Program counter bits #11~#0: Instruction code bits Rev. 2.30 HT46R63/HT46C63 When executing a jump instruction, conditional skip ex- ecution, loading PCL (program counter lower-order byte register), subroutine call, initial reset, interrupts or return from subroutine or interrupts, the program counter ma- nipulates the program transfer by loading the address corresponding to each instruction ...
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... The acti- Table Location * Table Location P11~P8: Current program counter bits 8 HT46R63/HT46C63 * March 22, 2006 ...
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... SET [m].i and CLR [m].i , respectively. They are also indirectly acces- sible through memory pointers (MP0 and MP1). Rev. 2.30 HT46R63/HT46C63 RAM Mapping Indirect Addressing Register Location 00H (02H) is indirect addressing registers that are not physically implemented. Any read/write opera- tion of [00H] ([02H]) will access data memory pointed to by MP0 (MP1) ...
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... Any data written into the status register will not change the TO or PDF flag. In addi- Rev. 2.30 HT46R63/HT46C63 Function Status (0AH) Register tion operations related to the status register may give different results from those intended. The TO flag ...
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... The related interrupt request flag will be reset and the EMI bit cleared to disable further inter- rupts. Rev. 2.30 HT46R63/HT46C63 During the execution of an interrupt subroutine, other in- terrupt acknowledgments are held until the RETI in- struction is executed or the EMI bit and the related interrupt control bit are set to 1 (of course, if the stack is not full) ...
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... The external resistor and capacitor components connected to the 32768Hz crystal are not necessary to pro- vide oscillation. For applications where precise RTC frequencies are essential, these components may be re- quired to provide frequency compensation due to different crystal manufacturing tolerances. Rev. 2.30 HT46R63/HT46C63 Function INTC0 (0BH) Register Function INTC1 (1EH) Register and the resistance should range from 24k to 1M ...
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... CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In the Rev. 2.30 HT46R63/HT46C63 case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLR WDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip as a result of time-out ...
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... The chip reset statuses of the functional units are as shown. (sys- SYS Program Counter 000H Interrupt Disable Clear. After master reset, WDT WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer Points to the top of the stack 14 HT46R63/HT46C63 March 22, 2006 ...
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... TMRH operations and writing TMRL will keep the timer/event counter preload register un- changed. Rev. 2.30 HT46R63/HT46C63 Reading TMRH will also latch the TMRL into the low byte buffer to avoid the false timing problem. Reading TMRL returns the contents of the low byte buffer. In other words, the low byte of timer/event counter cannot be read directly ...
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... HT46R63/HT46C63 WDT Time-out (HALT) (HALT)* uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu ...
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... To function as an in- put, the corresponding latch of the control register has to be set The pull-high resistor (if the pull-high re- Rev. 2.30 HT46R63/HT46C63 Function TMRC (0EH) Register Timer/Event Counter sistor is enabled) will be exhibited automatically. The in- put sources are also dependent on the control register ...
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... Once the comparator is disabled, the CHGO and CMPO will stay at VSS level. Rev. 2.30 HT46R63/HT46C63 Input/Output Ports LCD Display Memory The microcontroller provides an area of embedded data memory for LCD driver. This area is located from 40H to 53H of he RAM Bank 1. Bank pointer (BP ...
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... If LCD is turned on at HALT mode, the LCD outputs are dependent on LCD display memory. If LCD is turned off at HALT mode, the power will be V3=V2=V1=V0=VDD Rev. 2.30 HT46R63/HT46C63 and SEG15~SEG18 can be optioned individually. Once an LCD segment is optioned as a logical output, the con- tents of bit 0 of the related segment address in LCD RAM will appear on the segment ...
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... PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and Rev. 2.30 HT46R63/HT46C63 pull-high resistor of this I/O line are disabled. The EOCB bit (bit 6 of the ADCR) is end of A/D conversion flag. Check this bit to know when A/D conversion is com- pleted ...
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... Undefined Comparator control (*) 2 CMPC 0: Disable 1: Enable 3~6 Unused bit, read TEST For test mode used only Note: * This bit is 0 during reset. Rev. 2.30 HT46R63/HT46C63 Bit4 Bit3 Bit2 ADR (21H) Register Functions ADCR (22H) Register Functions ACSR (23H) Register 21 Bit1 Bit0 ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 2.30 HT46R63/HT46C63 /8 as the A/D clock SYS /8 as the A/D clock SYS 22 March 22, 2006 ...
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... Otherwise the PDi will stay The PWM modulation frequency, PWM cycle frequency and PWM cycle duty 1 are summarized in the following table SYS PWMi Modulation PWMi Cycle Frequency Frequency f /64 SYS PWM Mode 23 HT46R63/HT46C63 PWMi Cycle Duty f /256 [PWM]/256 SYS March 22, 2006 ...
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... LCD bias current: Low/Middle/High driving current LCD driver clock selection. 19 There are seven types of frequency signals for the LCD driver circuits: f clock source selection by options. Note stopped at HALT; RTCOSC(32.768kHz crystal) and WDT OSC are stopped or non-stopped at HALT decided by option(17). Rev. 2.30 HT46R63/HT46C63 Options ): ...
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... The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 2.30 HT46R63/HT46C63 C1 0pF 10k ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 2.30 Description 26 HT46R63/HT46C63 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 2.30 Description 27 HT46R63/HT46C63 Instruction Flag Cycle Affected 2 None (2) 1 None ...
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... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 2.30 PDF PDF PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 2.30 PDF PDF PDF addr PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 2.30 PDF PDF PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 2.30 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 2.30 Program Counter+1 PDF PDF PDF addr PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 2.30 PDF PDF Program Counter+1 PDF PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 2.30 Stack PDF Stack PDF Stack PDF PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF HT46R63/HT46C63 March 22, 2006 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 2.30 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 2.30 PDF PDF PDF ([m] 1) PDF ([m] 1) PDF HT46R63/HT46C63 March 22, 2006 ...
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... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 2.30 PDF PDF ([m]+1) PDF ([m]+1) PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 2.30 PDF PDF PDF [m].7~[m].4 PDF [m].7~[m].4 [m].3~[m].0 PDF HT46R63/HT46C63 March 22, 2006 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 2.30 PDF PDF PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 2.30 PDF PDF PDF HT46R63/HT46C63 March 22, 2006 ...
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... Package Information 56-pin SSOP (300mil) Outline Dimensions Symbol Rev. 2.30 Dimensions in mil Min. Nom. 395 291 8 720 HT46R63/HT46C63 Max. 420 299 12 730 March 22, 2006 ...
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... QFP (14´20) Outline Dimensions Symbol Rev. 2.30 Dimensions in mm Min. Nom. 18.50 13.90 24.50 19.90 0.65 0.30 2.50 0. HT46R63/HT46C63 Max. 19.20 14.10 25.20 20.10 3.10 3.40 1.40 0.20 7 March 22, 2006 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.30 HT46R63/HT46C63 43 March 22, 2006 ...