HT46R63 Holtek Semiconductor Inc., HT46R63 Datasheet - Page 14

• Manufacturer Part Number: HT46R63
• Description: Ht46r63/ht46c63 -- A/d With Lcd Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others keep their origi-
nal status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the option. Awakening from an I/O port stimu-
lus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 t
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
The 32.768kHz crystal oscillator still run or stop in the
halt mode. (decided by option)
Rev. 2.30
The system oscillator will be turned off but the
WDTOSC or RTCOSC will stop or keep running de-
cided by option (If the WDTOSC or RTCOSC is se-
lected)
The contents of the on-chip RAM and registers remain
unchanged.
WDT will be cleared and recounted again (if the WDT
clock is from the WDTOSC or RTCOSC).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
SYS
(sys-
14
Reset
There are three ways in which a reset can occur:
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a warm re -
set that resets only the program counter and SP, leav-
ing the other circuits in their original state. Some regis-
ters remain unchanged during other reset conditions.
Most registers are reset to the initial condition when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
Note: u means unchanged
To guarantee that the system oscillator is started and
stabilized, the SST (system start-up timer) provides an
extra-delay to delay 1024 system clock pulses when
system power-up or the system awakes from the HALT
state.
When the system power-up occurs, the SST delay is
added during the reset period. But when the reset co-
mes from the RES pin, the SST delay is disabled. Any
wake-up from HALT will enable the SST delay.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The chip reset statuses of the functional units are as
shown.
chip resets .
Program Counter
Interrupt
WDT
Timer/Event Counter Off
Input/Output Ports
Stack Pointer
TO PDF
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
0
u
0
1
1
0
u
1
u
1
RES reset during power-up
RES reset during normal operation
RES wake-up HALT
WDT time-out during normal operation
WDT wake-up HALT
Reset Conditions
000H
Disable
Clear. After master reset, WDT
begins counting
Input mode
Points to the top of the stack
HT46R63/HT46C63
March 22, 2006