HT46RU22 Holtek Semiconductor Inc., HT46RU22 Datasheet - Page 12

• Manufacturer Part Number: HT46RU22
• Description: Ht46ru22 -- A/d Type 8-bit Mcu
• Manufacturer: Holtek Semiconductor Inc.

perature, VDD and process variations. By selection the
WDT options, longer time-out periods can be realized. If
the WDT time-out is selected 2
period is divided by 2
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
The WDT overflow under normal operation will initialize
HALT mode, the overflow will initialize a warm reset only
the program counter and stack pointer are reset to 0. To
clear the contents of WDT, three methods are adopted; ex-
ternal reset (a low level to RES), software instructions, or a
HALT instruction. The software instructions include CLR
WDT and the other set CLR WDT1 and CLR WDT2. Of
these two types of instruction, only one can be active de-
pending on the options
tion . If the CLR WDT is selected (i.e. CLRWDT times
equal 1), any execution of the CLR WDT instruction will
clear the WDT. In case CLR WDT1 and CLR WDT2
are chosen (i.e. CLRWDT times equal two), these two in-
structions must be executed to clear the WDT; otherwise,
the WDT may reset the chip because of time-out.
If the WDT time-out period is selected f
WDT time-out period ranges from f
tions only clear the last two stages of the WDT.
Power Down Operation - HALT
The HALT mode is initialized by the HALT instruction
and results in the following...
Rev. 1.20
chip reset and set the status bit TO. Whereas in the
CLR WDT or CLR WDT1 and CLR WDT2 instruc-
The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is se-
lected).
The contents of the on chip RAM and registers remain
unchanged.
WDT will be cleared and recounted again (if the WDT
clock is from the WDT oscillator).
All of the I/O ports maintain their original status.
The PDF flag is set and the TO flag is cleared.
15
~2
16
CLR WDT times selection op-
about 2.1s~4.3s.
15
, the maximum time-out
s
/2
s
12
/2
~f
12
s
/2
(options), the
13
, since the
12
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a warm reset . After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the CLR WDT instruction and is set when execut-
ing the HALT instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and stack pointer; the others keep
their original status.
The port A wake-up and interrupt methods can be con-
sidered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stim-
ulus, the program will resume execution of the next in-
struction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is dis-
abled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regu-
lar interrupt response takes place. If an interrupt request
flag is set to 1 before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 t
tem clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
HT46RU22
March 23, 2007
SYS
(sys-