HT36F2 Holtek Semiconductor Inc., HT36F2 Datasheet

no-image

HT36F2

Manufacturer Part Number
HT36F2
Description
Ht36f2 -- Music Synthesizer 8-bit Mcu
Manufacturer
Holtek Semiconductor Inc.
Datasheet
Technical Document
Features
General Description
The HT36F2 is an 8-bit high performance RISC archi-
tecture microcontroller specifically designed for various
music applications. It provides an 8-bit MCU and a
4-channel Wavetable synthesizer. It has a built-in 8-bit
Block Diagram
Rev. 1.00
Tools Information
FAQs
Application Note
Operating voltage: 2.4V~5.0V
Operating frequency:
Xtal: 6MHz~8MHz
R
Built-in 32K 16-bit (0.5M-bit) ROM for program/data
shared
Built-in 8 bit MCU with 208 8 bits RAM
Two 8 bit programmable timer with 8 stage prescaler
16 bidirectional I/O lines
Four polyphonic synthesizer
Mono 16-bit DAC
OSC
: typ. 6MHz
Music Synthesizer 8-Bit MCU
1
microprocessor which controls the synthesizer to gen-
erate the melody by setting the special register. A HALT
feature is provided to reduce power consumption.
Oscillation modes: XTAL/RCOSC
Low voltage reset
Eight-level subroutine nesting
Watchdog timer
Supports 8-bit table read instruction (TBLP)
HALT function and wake-up feature reduce power
consumption
Bit manipulation instructions
63 powerful instructions
All instructions in 1 or 2 machine cycles
16/28-pin SOP package
HT36F2
August 15, 2005

Related parts for HT36F2

HT36F2 Summary of contents

Page 1

... Two 8 bit programmable timer with 8 stage prescaler 16 bidirectional I/O lines Four polyphonic synthesizer Mono 16-bit DAC General Description The HT36F2 is an 8-bit high performance RISC archi- tecture microcontroller specifically designed for various music applications. It provides an 8-bit MCU and a 4-channel Wavetable synthesizer. It has a built-in 8-bit Block Diagram Rev ...

Page 2

... Pin Assignment Pad Assignment Chip size: 2135 * The IC substrate should be connected to VSS in the PCB layout artwork. Rev. 1.00 2 2385 ( m) 2 August 15, 2005 HT36F2 ...

Page 3

... Bidirectional 8-bit I/O port Reset input, active low XIN for X tal or ROSCIN for resistor by mask option XOUT or T1 DAC output interface +5.5V Storage Temperature ........................... 125 C SS +0.3V Operating Temperature .......................... HT36F2 Unit 514.500 625.100 725.100 835.700 935.700 1046.300 1041.550 1041.550 1041.550 1041 ...

Page 4

... Flag Sink Current OL V Input High Voltage for I/O Ports IH V Input Low Voltage for I/O Ports IL Rev. 1.00 Test Conditions Min. Typ. V Conditions DD 2.4 4 load (OSC= 6MHz 4.5V 0. HT36F2 Ta=25 C Max. Unit 0. August 15, 2005 ...

Page 5

... Function Description Execution Flow The system clock for the HT36F2 is derived from either a crystal oscillator. The oscillator frequency di- vided the system clock for the MCU and it is inter- nally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. ...

Page 6

... It should be note that the PF reg- ister has to be cleared before setting to output mode. Wavetable ROM The ST15~ST0 is used to defined the start address of each sample on the wavetable and read the waveform data from the location. HT36F2 provides 16 output ad- Table Location * ...

Page 7

... The remaining space before the 30H is re- served for future expanded usage and reading these lo- cations will return the result 00H. The general purpose data memory, addressed from 30H to FFH, is used for data and control information under instruction com- mand. 7 August 15, 2005 HT36F2 ...

Page 8

... Interrupt The HT36F2 provides two internal timer counter inter- rupts on each bank. The Interrupt Control register (INTC;0BH) contains the interrupt control bits that sets the enable/disable and the interrupt request flags. ...

Page 9

... Oscillator Configuration The HT36F2 provides two types of oscillator circuit for the system clock e., RC oscillator and crystal oscillator. No matter what type of oscillator, the signal divided used for the system clock. The HALT mode stops the system oscillator and ignores external signal to con- serve power ...

Page 10

... CLR WDT in- struction will clear the WDT. In case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip be- cause of time-out. Watchdog Timer 10 HT36F2 Division Ratio 1:1 1:2 1:4 1:8 1:16 1:32 ...

Page 11

... The functional units chip reset status are shown below. Program Counter 000H Interrupt Disable Prescaler Clear (sys- SYS Clear. After master reset, WDT WDT begins counting Timer Counter (0/1) Off Input/output ports Input mode Stack Pointer Points to the top of stack Reset Timing Chart 11 HT36F2 August 15, 2005 ...

Page 12

... August 15, 2005 HT36F2 (HALT)* 0000H uuuu uuuu --11 uuuu -uuu uuuu uu-u 1uuu uu-u 1uuu ---- --uu ---- --uu uu-- --uu ---u uuuu u--u uuuu u--- uuuu ...

Page 13

... For example, the SET [m].i , CLR [m].i , CPL [m] and CPLA [m] instructions read the entire port states into the CPU, execute the defined op- erations (bit-operation), and then write the results back to the latches or the accumulator. Each line of port A has the capability to wake-up the device. 13 August 15, 2005 HT36F2 ...

Page 14

... No function, read only, read Unused: No function, read only, read CH1~CH0 channel number selection The HT36F2 has a built-in 8 output channels and CH1~CH0 is used to define which channel is selected. When this register is written to, the wavetable synthe- sizer will automatically output the dedicated PCM code ...

Page 15

... The PCM code definition The HT36F2 can only solve the voice format of the signed 8-bit or 12-bit raw PCM. And the MCU will take the voice code 80H as the end code. So each PCM code section must be ended with the end code 80H. · ...

Page 16

... Mask Option No. Mask Option 1 WDT source On-chip RC/Instruction clock/ disable WDT 2 CLRWDT times One time, two times (CLR WDT1/WDT2) 3 Wake-up PA only 4 Pull-High PA, PB, PC input 5 OSC mode Crystal or Resistor type 6 LVR Enable/disable 7 LVD 2.2V/3.3V Application Circuit Rev. 1.00 Function 16 August 15, 2005 HT36F2 ...

Page 17

... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.00 Instruction Description 17 HT36F2 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 ...

Page 18

... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Instruction Description 18 HT36F2 Flag Cycle Affected 2 None (2) 1 None ...

Page 19

... Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 1. HT36F2 August 15, 2005 ...

Page 20

... Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 1. addr HT36F2 August 15, 2005 ...

Page 21

... Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 1. HT36F2 August 15, 2005 ...

Page 22

... Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 1. (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C HT36F2 August 15, 2005 ...

Page 23

... Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 1.00 Program Counter addr HT36F2 August 15, 2005 ...

Page 24

... Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 1. Program Counter HT36F2 August 15, 2005 ...

Page 25

... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 1.00 Stack Stack Stack HT36F2 August 15, 2005 ...

Page 26

... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 1. HT36F2 August 15, 2005 ...

Page 27

... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev HT36F2 August 15, 2005 ...

Page 28

... Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 1. ([m]+ ([m]+ HT36F2 August 15, 2005 ...

Page 29

... The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 1. [m].7~[m].4 [m].3~[m]. HT36F2 August 15, 2005 ...

Page 30

... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 1. HT36F2 August 15, 2005 ...

Page 31

... Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 1. HT36F2 August 15, 2005 ...

Page 32

... Package Information 16-pin SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 390 Rev. 1.00 Dimensions in mil Nom. Max. 419 300 20 413 104 August 15, 2005 HT36F2 ...

Page 33

... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 697 Rev. 1.00 Dimensions in mil Nom. Max. 419 300 20 713 104 August 15, 2005 HT36F2 ...

Page 34

... Space Between Flange T2 Reel Thickness SOP 28W (300mil) Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Dimensions in mm 330 1 62 1.5 13 0.5 0.2 2 0.5 16.8+0.3 0.2 22.2 0.2 Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 34 August 15, 2005 HT36F2 ...

Page 35

... Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Dimensions 0.2 12 0.1 1.75 0.1 7.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.9 0.1 10.8 0.1 3 0.1 0.3 0.05 13.3 Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 35 August 15, 2005 HT36F2 ...

Page 36

... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 36 August 15, 2005 HT36F2 ...

Related keywords