HT37Q70 Holtek Semiconductor Inc., HT37Q70 Datasheet - Page 25

• Manufacturer Part Number: HT37Q70
• Description: 4-channel Music Synthesizer Mcu
• Manufacturer: Holtek Semiconductor Inc.

Watchdog Timer Register - WDTS
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ra-
tios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate divi-
sion ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set divi-
sion ratios between 1 and 128.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system manage-
ment flags are used to record the status and operation of
the microcontroller.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, opera-
tions related to the status register may give different re-
sults due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the CLR WDT or HALT in-
struction. The PDF flag is affected only by executing the
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Rev. 1.00
HALT or CLR WDT instruction or during a system
C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place dur-
ing a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
Status Register
25
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Interrupt Control Registers - INTC, INTCH
The two 8-bit registers, known as the INTC and INTCH
register which control the operation of both external and
internal timer, CR/F and ADPCM interrupts, and By set-
ting various bits within this register using standard bit
manipulation instructions, the enable/disable function of
the external and timer, CR/F and ADPCM interrupts can
be independently controlled. A master interrupt bit within
this register, the EMI bit, acts like a global enable/dis-
able and is used to set all of the interrupt enable bits on
or off. This bit is cleared when an interrupt routine is en-
tered to disable further interrupt and is set by executing
the RETI instruction.
Note: In situations where other interrupts may require
AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nib-
ble into the low nibble in subtraction; otherwise AC is
cleared.
Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
PDF is cleared by a system power-up or executing the
TO is cleared by a system power-up or executing the
WDT time-out.
CLR WDT instruction. PDF is set by executing the
HALT instruction.
CLR WDT or HALT instruction. TO is set by a
servicing within present interrupt service rou-
tines, the EMI bit can be manually set by the pro-
gram after the present interrupt service routine
has been entered.
HT37Q70/60/50/40/30/20
February 17, 2009