HT6523 Holtek Semiconductor Inc., HT6523 Datasheet - Page 3

• Manufacturer Part Number: HT6523
• Description: Ps/2 Mouse Controller
• Manufacturer: Holtek Semiconductor Inc.

A.C. Characteristics
Functional Description
Power-on Reset
The Mouse logic generates a power-on reset at power
up after 600 millisecond ± 20%.
Modes of Operation
·
·
·
·
Data Transmission
During data transmission, CLK is used to clock serial
data. The mouse generates a clocking signal when
sending data to and receiving data from the system. The
system requests the mouse receiving system data out-
put by forcing the data line to an inactive level and allow-
ing CLK to go to an active level.
Communication is bidirectional using the clock and data
signal lines. The signal for each of these lines comes
from open collector devices, allowing either the mouse
or the system to force a line to an inactive level. During a
non-transmission state, CLK and DATA are both held at
an active level.
·
Rev. 1.20
Symbol
Reset
After power up or when receiving a reset command,
CLK and DATA lines can go to a positive level. The
mouse waits between 300 to 500 milliseconds and
sends AA to the host, followed by a device ID of 00.
After reset the mouse is set to its default values: Incre-
mental stream mode, 1:1 scaling, report rate of 100, 6
counts per mm at 320 DPI or 4 counts per mm at 200
DPI, and then disable itself. No further action occurs
until a command is sent from the host.
Stream
In this mode, a data report is transmitted to the system
if a switch is pressed or released, or if at least one
count of movement has been detected. The maximum
rate of transfer is the programmed sample rate.
Remote
In this mode, data is transmitted only in response to a
read data command.
Wrap
In this mode, any byte of data sent by the system, ex-
cept hex EC or hex FF, is returned by the mouse.
Data output
When the mouse is ready to transmit, it checks for an
inhibit signal or a host request-to-send status on CLK
and DATA. If CLK is low, data is continuously updated
t
f
SYS
RES
System Clock (RC OSC)
External Reset Low Pulse Width
Parameter
3V
5V
3V
R
R
Test Conditions
3
OSC
OSC
·
=120K
=120K
in the mouse and no transmissions are made. If CLK
is high and DATA is low (request-to-send), the data is
also updated in the mouse, the mouse inputs the host
data, and no transmissions are started by the mouse
until CLK and DATA are both high. If CLK and DATA
are both high, the mouse proceeds to output 0 start
bit, 8 data bits, parity bit, and stop bit if a transmission
is required. Data is valid prior to the falling edge of
CLK and beyond the rising edge of CLK. During trans-
mission, the mouse checks for a line contention by
checking for an inactive level on CLK at intervals not
to exceed 100 ms. Contention occurs when the host
lowers CLK to inhibit the mouse output after the
mouse starts a transmission. If this occurs before the
rising edge of the tenth clock (parity bit), the mouse in-
ternally stores its data packet in the mouse buffer and
returns both DATA and CLK high. If there is no con-
tention by the tenth clock, the mouse completes the
transmission. Following a transmission, the host can
inhibit the mouse until it services the input or until it re-
quests to send a response if necessary.
Data input
When the host is ready to send data to the mouse, it
first checks to see if the mouse is transmitting data. If
the mouse is transmitting, the host can override the
mouse output by forcing CLK low before the tenth
clock. If the mouse transmits beyond this, the host re-
ceives the data. If the mouse is not transmitting or if
the host overrides the mouse output, the host forces
CLK to an inactive level for a period of not less than
100 ms while preparing for output. When the system is
ready to output 0 start bit (data line is low), it allows
CLK to go to an active level. The mouse checks this
state every 10ms.
If request-to-send is detected, the mouse clocks 11
bits. After the tenth clock, the mouse checks for a high
on the DATA line and if found, the mouse forces DATA
to a low level and clocks once more. This signals the
host to return to the ready state when it can accept in-
put or go to an inhibit mode until ready. If DATA is
found at an inactive level following clock 10, a framing
error has occurred and the mouse continues to clock
until DATA is high, then clocks the line control bit and
request a resend. For host commands and data trans-
mission that requires a response, the host waits for
the mouse to respond before sending its next output.
¾
Min.
5.4
5.4
1
Typ.
¾
6
6
Max.
March 6, 2003
6.6
6.6
¾
HT6523
Unit
MHz
MHz
ms