HT56R66 Holtek Semiconductor Inc., HT56R66 Datasheet - Page 43
HT56R66
Manufacturer Part Number
HT56R66
Description
Tinypower Tm A/d Type With Lcd 8-bit Otp Mcu
Manufacturer
Holtek Semiconductor Inc.
Datasheet
1.HT56R66.pdf
(104 pages)
- Current page: 43 of 104
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Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal inter-
rupt signal each time the Timer/Event Counter over-
flows. To operate in this mode, the Operating Mode
Select bit pair, TnM1/TnM0, in the Timer Control Regis-
ter must be set to the correct value as shown.
In this mode the internal clock, f
nal clock for 8-bit Timer/Event Counter 0 and f
f
Counter 1. However, the clock source, f
timer is further divided by a prescaler, the value of which
is determined by the Prescaler Rate Select bits
TnPSC2~TnPSC0, which are bits 2~0 in the Timer Con-
trol Register. After the other bits in the Timer Control
Register have been setup, the enable bit TnON or
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run.
Each time an internal clock cycle occurs, the
Timer/Event Counter increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the corre-
sponding Interrupt Control Register, is reset to zero.
Rev. 1.10
Control Register Operating Mode
Select Bits for the Timer Mode
SYS
/4 is used as the internal clock for 16-bit Timer/Event
SYS
Timer/Event Counter Control Register - TMRnC
, is used as the inter-
SYS
, for the 8-bit
Bit7 Bit6
Timer Mode Timing Chart
1
SUB
0
or
43
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TnM1/TnM0,
in the Timer Control Register must be set to the correct
value as shown.
In this mode, the external timer pin, is used as the
Timer/Event Counter clock source, however it is not di-
vided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TnON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run. If
the Active Edge Select bit, TnE, which is bit 3 of the
Timer Control Register, is low, the Timer/Event Counter
will increment each time the external timer pin receives
a low to high transition. If the Active Edge Select bit is
high, the counter will increment each time the external
timer pin receives a high to low transition. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the corre-
sponding Interrupt Control Register, is reset to zero.
Control Register Operating Mode
Select Bits for the Event Counter Mode
HT56R66/HT56R666
September 8, 2009
Bit7 Bit6
0
1
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