RF31 Hope Microelectronics co., Ltd, RF31 Datasheet
RF31
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RF31 Summary of contents
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... Wireless PC peripherals The RF31 offers advanced radio features including continuous frequency coverage from 240–960 MHzThe RF31‘s high level of integration offers reduced BOM cost while simplifying the overall system design. The extremely low receive sensitivity (–118 dBm) ensures extended range and improved link performance. Built-in antenna diversity and support for frequency hopping can be used to further extend range and enhance performance ...
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Functional Block Diagram Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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T C ABLE OF ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Layout Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … … .62 11.3. Matching Network Design . . . . . . . . . . . . . . . . . . . . . … … .63 12. Reference Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … .64 12.1. Complete Register Table and Descriptions . . . . . . . . . . … … .64 13. Pin Descriptions: RF31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . … ... . … .134 14. Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … … .136 15. Errata Status Summary......................................................................................................137 16.Errata Details.......................................................................................................................138 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . … .139 ...
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Electrical Specifications Table 1. DC Characteristics Parameter Symbol Supply Voltage Range V dd Power Saving Modes I Shutdown I Standby I Sleep ISensor- LBD ISensor Ready TUNE Mode Current I Tune RX Mode Current I RX Notes: ...
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Table 2. Synthesizer AC Electrical Characteristics Parameter Symbol Synthesizer Frequency F SYNTH-LB Range F SYNTH-HB F Synthesizer Frequency RES-LB 2 Resolution F RES-HB Reference Frequency f REF Reference Frequency f REF_LV 2 Input Level Synthesizer Settling t 2 Time LOCK ...
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Table 3. Transmitter AC Electrical Characteristics Parameter Symbol F SYNTH-LB RX Frequency Range F SYNTH-HB RX Sensitivity P RX_2 P RX_40 P RX_100 P RX_125 P RX_OOK Bandwidth Residual BER P RX_RES 2 Performance rd Input Intercept ...
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Table 4. Auxiliary Block Specifications Parameter Symbol Temperature Sensor TS 2 Accuracy Temperature Sensor TS 2 Sensitivity Low Battery Detector LBD 2 Resolution Low Battery Detector LBD 2 Conversion Time Microcontroller Clock Output Frequency MC General Purpose ADC ADC 2 ...
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Table 5. Digital IO Specifications (SDO, SDI, SCLK, nSEL, and nIRQ) Parameter Rise Time Fall Time Input Capacitance Logic High Level Input Voltage Logic Low Level Input Voltage Input Current Logic High Level Output Voltage Logic Low Level Output Voltage ...
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Table 7. Absolute Maximum Ratings Parameter V to GND DD Voltage on Digital Control Inputs Voltage on Analog Inputs RX Input Power Operating Ambient Temperature Range T Thermal Impedance θ JA Junction Temperature T J Storage Temperature Range T STG ...
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... DD External reference signal (XIN) = 0.7 to 1.6 V Production test schematic (unless noted otherwise) All RF input and output levels referred to the pins of the RF31 (not the RF module) Test Notes: All electrical parameters with Min/Max values are guaranteed by one (or more) of the following test methods. Electrical parameters shown with only Typical values are not guaranteed. ...
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... Antenna diversity is completely integrated into the RF31 and can improve the system link budget by 8–10 dB, resulting in substantial range increases depending on the environmental conditions. The RF31 is designed to work with a microcontroller, crystal, and a few passives to create a very low cost system. Voltage regulators are integrated on-chip which allow for a wide range of operating supply voltage conditions from +1 ...
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... Depending upon the system communication protocol, the optimal trade-off between the radio wake time and power consumption can be achieved. Table 8 summarizes the modes of operation of the RF31. In general, any given mode of operation may be classified as an Active mode or a Power Saving mode. The table indicates which block(s) are enabled (active) in each corresponding mode. With the exception the Shutdown mode, all can be dynamically selected by sending the appropriate commands over the SPI in order to optimize the average current consumption. An ― ...
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... Select high period SW To read back data from the RF31, the R/W bit must be set to 0 followed by the 7-bit address of the register from which to read. The 8 bit DATA field following the 7-bit ADDR field is ignored when R The next eight negative edge transitions of the SCLK signal will clock out the contents of the selected register. The data read from the selected register will be available on the SDO output pin ...
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... ADDR and read from/write to the next address. An SPI burst write transaction is demonstrated in Figure 4 and burst read in Figure 3. As long as nSEL is held low, input data will be latched into the RF31 every eight SCLK cycles. A burst read transaction is also demonstrated in Figure 5. Tel: +86-755-82973805 Figure 3. SPI Timing— ...
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... Operating Mode Control There are three primary states in the RF31 radio state machine: SHUTDOWN, IDLE, and RX (see Figure 6). The SHUTDOWN state completely shuts down the radio to minimize current consumption. There are five different configurations/options for the IDLE state which can be selected to optimize the chip to the applications needs. ...
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Shutdown State The shutdown state is the lowest current consumption state of the device with nominally less than current consumption. The shutdown state may be entered by driving the SDN pin (Pin 20) high. The SDN ...
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Enable the Main Digital LDO and the Analog LDOs. 2. Start up crystal oscillator and wait until ready (controlled by timer). 3. Enable PLL. 4. Calibrate VCO (this action is skipped when the vcocal bit is ―0‖, default value ...
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... Interrupts The RF31 is capable of generating an interrupt signal when certain events occur. The chip notifies the microcontroller that an interrupt event has been detected by setting the nIRQ output pin LOW = 0. This interrupt signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits) shown below occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Register(s) (Registers 03h– ...
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System Timing The system timing for RX mode is shown in Figure small range of frequencies is being used and the temperature range is fairly constant a calibration may only be needed at the initial power ...
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... Frequency Control 3.6.1. Frequency Programming In order to transmit an RF signal, the desired channel frequency, fcarrier, must be programmed into the RF31.Note that this frequency is the center frequency of the desired channel and not an LO frequency. The carrier frequency is generated by a Fractional-N Synthesizer, using 10 MHz both as the reference frequency and the clock of the (3 modulator uses modulo 64000 accumulators ...
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Value The chip will automatically shift the frequency of the Synthesizer down by 937.5 kHz ...
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... Easy Frequency Programming for FHSS While Registers 73h–77h may be used to program the carrier frequency of the RF31 often easier to think in terms of ―channels‖ or ―channel numbers‖ rather than an absolute frequency value in Hz. Also, there may be some timing-critical applications (such as for Frequency Hopping Systems) in which it is desirable to change frequency by programming a single register. Once the channel step size is set, the frequency may be changed by a single register corresponding to the channel number. A nominal frequency is first set using Registers 73h– ...
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The previous equation should be used to calculate the desired frequency deviation. If desired, frequency modulation may also be disabled in order to obtain an unmodulated carrier signal at the channel center frequency; see "4.1. Modulation Type" for further details. ...
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Frequency Offset Adjustment When the AFC is disabled the frequency offset can be adjusted manually by fo[9:0] in registers 73h and 74h. The frequency offset adjustment and the AFC both are implemented by shifting the Synthesizer Local Oscillator frequency. ...
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The AFC function shares registers 73h and 74h with the Frequency Offset setting. If AFC is enabled (D6 in ―Register 1Dh. AFC Loop Gearshift Override,‖), the Frequency Offset shows the results of the AFC algorithm for the current receive slot. ...
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Modulation Options 4.1. FIFO Mode In FIFO mode, the integrated FIFO is used to receive the data. The FIFO is accessed via "Register 7Fh. FIFO Access" with burst read capability. The FIFO may be configured specific to the application ...
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Internal Functional Blocks This section provides an overview some of the key blocks of the internal radio architecture. 5.1. RX LNA The input frequency range for the LNA is 240–960 MHz. The LNA provides gain with a noise figure ...
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The Invalid Preamble Detector issues an interrupt when no valid preamble signal is found. After the receiver is enabled, the Invalid Preamble Detector output is ignored for 16 Tb (Where Tb is the time of a bit duration) to allow ...
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... Crystal Oscillator The RF31 includes an integrated 30 MHz crystal oscillator with a fast start-up time of less than 600 μs when a suitable parallel resonant crystal is used. The design is differential with the required crystal load capacitance integrated on-chip to minimize the number of external components ...
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Data Handling and Packet Handler 6.1. RX FIFO A 64 byte FIFO is integrated into the chip for RX, as shown in Figure 11. "Register 7Fh. FIFO Access" is used to access the FIFO. A burst read, as described ...
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Packet Configuration When using the FIFO, automatic packet handling may be enabled for the RX mode. "Register 30h. Data Access Control" through ―Register 39h. Synchronization Word 0,‖ and ―Register 3Fh. Check Header 3,‖ through ―Register 4Bh. Received Packet Length,‖ ...
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Figure 14. Multiple Packets in RX Packet Handler Figure 15. Multiple Packets in RX with CRC or Header Error Table 12. RX Packet Handler Configuration FIFO_PH 10 1 FIFO 10 0 Direct 0X X Tel: +86-755-82973805 option set option — ...
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Table 13. Packet Handler Registers Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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... Figure 16. Operation of Data Whitening, Manchester Encoding, and CRC 6.5. Preamble Detector The RF31 has integrated automatic preamble detection. The preamble length is configurable from 1–256 bytes using the prealen[7:0] field in "Register 33h. Header Control 2" and "Register 34h. Preamble Length", as described in ―6.2. Packet Configuration‖ ...
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Mode (G)FSK AFC Disabled (G)FSK AFC Enabled (G)FSK AFC Disabled +Antenna Diversity Enabled (G)FSK AFC Enabled +Antenna Diversity Enabled OOK OOK + Antenna Diversity Enabled Note: The recommended preamble length and the preamble detection threshold may be shortened when occasional ...
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RX Modem Configuration 7.1. Modem Settings for FSK and GFSK The modem performs channel selection and demodulation in the digital domain. The channel filter bandwidth is configurable from 620 to 2.6 kHz. The data-rate, modulation index, and bandwidth are ...
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Advanced FSK and GFSK Settings In nearly all cases, the information in Table 15, ―RX Modem Configurations for FSK and GFSK,‖ can be used to determine the required FSK and GFSK modem parameters. The section includes a more detailed ...
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Table 16. Filter Bandwidth Parameters BW ndec_exp dwn3_bypass [kHz] 1C-[6:4] 1C-[ 5.9 4 ...
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... Modem Settings for OOK The RF31 is configured for OOK mode by setting the modtyp[1:0] field to OOK in "Register 71h. Modulation Mode Control 2". In OOK mode, the following parameters can be configured: data rate, manchester coding, channel filter bandwidth, and the clock recovery oversampling rate. ...
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The clock recovery oversampling rate is set via rxosr[10:0] in "Register 20h. Clock Recovery Oversampling Rate" and "Register 21h. Clock Recovery Offset 2". ndec_exp and dwn3_bypass together with the receive data rate (Rb) are used to calculate rxosr: Where: Rb ...
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Table 19. RX Modem Configuration for OOK with Manchester Disabled RX Modem Setting Examples for OOK (Manchester Disabled) Appl Parameters Rb Fd dwn3_bypass [kbps] [kHz] 1Ch 1 1.2 110 0 1.2 335 1 1.2 420 1 1.2 620 ...
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... Auxiliary Functions 8.1. Smart Reset The RF31 contains an enhanced integrated SMART RESET or POR circuit. The POR circuit contains both a classic level threshold reset as well as a slope detector POR. This reset circuit was designed to produce reliable reset signal in any circumstances. Reset will be initiated if any of the following conditions occur: ...
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... If the microcontroller clock option is being used there may be the need of a System Clock for the microcontroller while the RF31 is in SLEEP mode. Since the Crystal Oscillator is disabled in SLEEP mode in order to save current, the low-power 32.768 kHz clock can be automatically switched to become the microcontroller clock. This feature is called Enable Low Frequency Clock and is enabled by the enlfc bit ...
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General Purpose ADC An 8-bit SAR ADC is integrated onto the chip for general purpose use, as well as for digitizing the temperature sensor reading. ―Register 0Fh. ADC Configuration,‖ must be configured depending on the use of the GP ...
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ADC Differential Input Mode—Bridge Sensor Example The differential input mode of ADC8 is designed to directly interface any bridge-type sensor, which is demonstrated in the figure below. As seen in the figure the use of the ADC in this ...
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The differential offset can be coarse compensated by the adcoffs[3:0] bits found in "Register 11h. ADC Value". Fine compensation should be done by the microcontroller software. The main reason for the offset compensation is to shift the negative offset voltage ...
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Temperature Sensor An analog temperature sensor is integrated into the chip. The temperature sensor will be automatically enabled when the temperature sensor is selected as the input of the ADC or when the analog temp voltage is selected on ...
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Figure 21. Temperature Ranges using ADC8 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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Low Battery Detector A low battery detector (LBD) with digital read-out is integrated into the chip. A digital threshold may be programmed into the lbdt[4:0] field in "Register 1Ah. Low Battery Detector Threshold". When the digitized battery voltage reaches ...
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Wake-Up Timer The chip contains an integrated wake-up timer which periodically wakes the chip from SLEEP mode. The wake-up timer runs from the internal 32.768 kHz RC Oscillator. The wake-up timer can be configured to run when in SLEEP ...
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Figure 22. WUT Interrupt and WUT Operation Tel: +86-755-82973805 Fax: +86-755-82973550 Interrupt Enable enwut=1 (Reg 06h) Interrupt Enable enwut=0 (Reg 06h) E-mail: sales@hoperf.com http://www.hoperf.com ...
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Low Duty Cycle Mode The Low Duty Cycle Mode is available to automatically wake-up the receiver to check if a valid signal is available. The basic operation of the low duty cycle mode is demonstrated in the figure below. ...
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GPIO Configuration Three general purpose IOs (GPIOs) are available. Numerous functions such as specific interrupts, Antenna Diversity Switch control, Microcontroller Output, etc. can be routed to the GPIO pins as shown in the tables below. When in Shutdown mode ...
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Antenna-Diversity To mitigate the problem of frequency-selective fading due to multi-path propagation, some radio systems use a scheme known as Antenna Diversity. In this scheme, two antennas are used. Each time the radio enters RX mode the receive signal ...
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RSSI and Clear Channel Assessment The RSSI (Received Signal Strength Indicator) signal is an estimate of the signal strength in the channel to which the receiver is tuned. The RSSI value can be read from an 8-bit register with ...
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Reference Design Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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... C11 CPOL-USCT3216 C12 100 pF C-USC0603K 1 μF C13 C-USC0603K C14 100 pF C-USC0603K C18 100 nF C-USC0603K C23 100 nF C-USC0603K CS1 CON40-0 CON40-0 IC1 RF31 IC2 25AA040ST 25AA040ST L6 * INDUCTCOILCRAFT-0603 Q1 30 MHz CRYSTAL Q2 32.7 kHz CRYSTAL R1 100 KΩ R-US_R0603 R2 10 KΩ R-US_R0603 R4 100 KΩ R-US_R0603 R5 10 KΩ ...
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Measurement Results Note: Sensitivity is BER measured, GFSK modulation 0. Tel: +86-755-82973805 Figure 29. Sensitivity vs. Data Rate Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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Figure 30. Receiver Selectivity Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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... RF31 RF31 Figure 31. Synthesizer Settling Time for 1 MHz Jump Settled within 10 kHz Figure 32. Synthesizer Phase Noise (VCOCURR = 11) Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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Application Notes 11.1. Crystal Selection The recommended crystal parameters are given in Table 25. Table 25. Recommended Crystal Parameters Frequency ESR 60Ω 30 MHz The internal XTAL oscillator will work over a range for the parameters of ESR, CL, ...
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Matching Network Design 11.3.1. RX LNA Matching Freq Band 915 MHz 868 MHz 434 MHz 315 MHz Tel: +86-755-82973805 Figure 33. RX LNA Matching Table 26. RX Matching for Different Bands C1 6.8 pF 11.0 nH 6.8 pF 11.0 ...
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Reference Material 12.1. Complete Register Table and Descriptions Tel: +86-755-82973805 Table 27. Register Descriptions Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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Table 27. Register Descriptions (Continued) Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com ...
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Register 00h. Device Type Code (DT) Bit D7 D6 Name Reserved Type Reset value = 00001000 Bit Name 7:5 Reserved 4:0 dt[4:0] Register 01h. Version Code (VC) Bit D7 D6 Name Reserved Type Reset value = xxxxxxxx Bit Name 7:5 ...
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Register 02h. Device Status Bit D7 D6 Name ffovfl ffunfl Type R R Reset value = xxxxxxxx Bit Name 7 ffovfl 6 ffunfl 5 rxffem 4 Reserved headerr 3:2 Reserved 1:0 cps[1:0] Tel: +86-755-82973805 rxffem headerr Reserved ...
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Register 03h. Interrupt/Status 1 Bit D7 D6 Name ifferr Reserved Type R R Reset value = xxxxxxxx Bit Name FIFO Underflow/Overflow Error. 7 ifferr When set to 1 the TX FIFO has overflowed or underflowed. 6:5 Reserved Reserved. RX FIFO ...
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Table 28. Interrupt or Status 1 Bit Set/Clear Description Status Bit Name 7 ifferr Set if there is a FIFO overflow or underflow. Cleared by applying FIFO reset. 6:5 Reserved Reserved. Set when the number of bytes in the RX ...
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Register 04h. Interrupt/Status 2 Bit D7 D6 Name iswdet ipreaval Type R R Reset value = xxxxxxxx Bit Name Sync Word Detected. 7 iswdet When a sync word is detected this bit will be set to 1. Valid Preamble Detected. ...
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Table 30. Interrupt or Status 2 Bit Set/Clear Description Bit Name Goes high once the Sync Word is detected. Goes low once we are done 7 iswdet receiving the current packet. Goes high once the preamble is detected. Goes low ...
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Register 05h. Interrupt Enable 1 Bit D7 D6 Name enfferr Reserved Type Reset value = 00000000 Bit Name Enable FIFO Underflow/Overflow. 7 enfferr When set to 1 the FIFO Underflow/Overflow interrupt will be enabled. 6:5 Reserved. ...
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Register 06h. Interrupt Enable 2 Bit D7 D6 Name enswdet enpreaval Type R R Reset value = 00000011 Bit Name Enable Sync Word Detected. 7 enswdet When mpreadet =1 the Preamble Detected Interrupt will be enabled. Enable Valid Preamble Detected. ...
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Register 07h. Operating Mode and Function Control 1 Bit D7 D6 Name swres enlbd Type Reset value = 00000001 Bit Name Software Register Reset Bit. This bit may be used to reset all registers simultaneously to ...
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Register 08h. Operating Mode and Function Control 2 Bit D7 D6 Name antdiv[2:0] Type w R/ Reset value = 00000001 Bit Name Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly. 7:5 ...
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Register 09h. 30 MHz Crystal Oscillator Load Capacitance Bit D7 D6 Name xtalshft Type w R/ Reset value = 01111111 Bit Name Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. 7 xtalshft Not binary with xlc[6:0]. ...
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Register 0Ah. Microcontroller Output Clock Bit D7 D6 Name Reserved Type R Reset value = xx000110 Bit Name 7:6 Reserved. Reserved Clock Tail. If enlfc = 0 then it can be useful to provide a few extra cycles for the ...
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Register 0Bh. GPIO Configuration 0 Bit D7 D6 Name gpiodrv0[1:0] Type w R/ Reset value = 00000000 Bit Name 7:6 gpiodrv0[1:0] 5 pup0 4:0 gpio0[4:0] Tel: +86-755-82973805 D5 D4 pup0 w R/ GPIO Driving Capability Setting. Pullup Resistor Enable on ...
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Register 0Ch. GPIO Configuration 1 Bit D7 D6 Name gpiodrv1[1:0] Type w R/ Reset value = 00000000 Bit Name 7:6 gpiodrv1[1:0] 5 Pup1 4:0 gpio1[4:0] Tel: +86-755-82973805 D5 D4 pup1 w R/ GPIO Driving Capability Setting. Pullup Resistor Enable on ...
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Register 0Dh. GPIO Configuration 2 Bit D7 D6 Name gpiodrv2[1:0] Type w R/ Reset value = 00000000 Bit Name 7:6 gpiodrv2[1:0] 5 Pup2 4:0 gpio2[4:0] Tel: +86-755-82973805 D5 D4 pup2 w R/ GPIO Driving Capability Setting. Pullup Resistor Enable on ...
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Register 0Eh. I/O Port Configuration Bit D7 D6 Name Reserved extitst[2] Type R R Reset value = 00000000 Bit Name 7 Reserved Reserved External Interrupt Status. 6 extitst[2] If the GPIO2 is programmed to be external interrupt sources then the ...
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Register 0Fh. ADC Configuration Bit D7 D6 adcstart/ Name adcdone w Type R/ Reset value = 00000000 Bit Name adcstart/adcdone 7 6:4 adcsel[2:0] 3:2 adcref[1:0] 1:0 adcgain[1:0] Tel: +86-755-82973805 adcsel[2: ADC Measurement Start Bit. Reading ...
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Register 10h. ADC Sensor Amplifier Offset Bit D7 D6 Name Reserved Type Reset value = xxxx0000 Bit Name 7：4 Reserved Reserved. 3：0 adcoffs[3:0] ADC Sensor Amplifier Offset*. *Note: The offset can be calculated as Offset = adcoffs[2:0] x VDD / ...
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Register 12h. Temperature Sensor Calibration Bit D7 D6 Name tsrange[1:0] Type w R/ Reset value = 00100000 Bit Name tsrange[1:0] Temperature Sensor Range Selection. (FS range is 0..1024 mV) 00: 7：6 01: 11: 10: 5 entsoffs Temperature Sensor Offset to ...
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Note new configuration is needed (e.g., for the WUT or the LDC), proper functionality is required. The function must first be disabled, then the settings changed, then enabled back on. Register 14h. Wake-Up Timer Period 1 Bit D7 ...
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Register 17h. Wake-Up Timer Value 1 Bit D7 D6 Name Type Reset value = xxxxxxxx Bit Name 7：0 wtm[15:8] *Note: The period of the wake-up timer can be calculated as T Register 18h. Wake-Up Timer Value 2 Bit D7 D6 ...
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Register 1Ah. Low Battery Detector Threshold Bit D7 D6 Name Reserved Type R Reset value = xxx10100 Bit Name 7：5 Reserved Reserved. Low Battery Detector Threshold. 4：0 lbdt[4:0] This threshold is compared to Battery Voltage Level. If the Battery Voltage ...
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Register 1Ch. Battery Voltage Level Bit D7 D6 Name dwn3_bypass Type R/W Reset value = 00000001 Bit Name Bypass Decimator by 3 (if set). dwn3_bypass 7 6:4 ndec_exp[2:0] IF Filter Decimation Rates. IF Filter Coefficient Sets. 3:0 filset[3:0] Defaults are ...
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Register 1Eh. AFC Timing Control Bit D7 D6 Name Reserved Type R Reset value = xx001010 Bit Name Reserved. Reserved 7:6 Short Wait Periods after AFC Correction. Used before preamble is detected. Short wait = (RegValue + ...
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Register 1Fh. Clock Recovery Gearshift Override Bit D7 D6 Name Reserved rxready Type R/W R/W Reset value = 00000011 Bit Name Reserved. Reserved 7 Improves Receiver Noise Immunity when in Direct Mode recommended to set this bit after ...
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Register 20h. Clock Recovery Oversampling Rate Bit D7 D6 Name Type Reset value = 01100100 Bit Name 7：0 rxosr[7:0] The oversampling rate can be calculated as rxosr = 500 kHz/(2 dwn3_bypass values found at Address: 1Ch – IF Filter Bandwidth ...
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Register 21h. Clock Recovery Offset 2 Bit D7 D6 Name rxosr[10:8] Type R/W Reset value = 00000001 Bit Name 7:5 rxosr[10:8] 4 stallctrl 3:0 ncoff[19:16] The offset can be calculated as follows: The default values for register 20h to 23h ...
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Register 23h. Clock Recovery Offset 0 Bit D7 D6 Name Type Reset value = 10101110 Bit Name 7:5 ncoff[7:0] Register 24h. Clock Recovery Timing Loop Gain 1 Bit D7 D6 Name Type Reset value = 00000010 Bit Name 7:3 Reserved ...
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Register 26h. Received Signal Strength Indicator Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 rssi [7:0] Register 27h. RSSI Threshold for Clear Channel Indicator Bit D7 D6 Name Type Reset value = 00011110 Bit Name 7:0 ...
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Register 29h. Antenna Diversity 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 adrssi2[7:0] Register 2Ah. AFC Limiter Bit D7 D6 Name Type Reset value = 00101010 Bit Name 7:0 Afclim[7:0] For the following registers (addresses ...
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Register 2Ch. OOK Counter Value 1 Bit D7 D6 Name afc_corr[1:0] Type R Reset value = 00101100 Bit Name 7:6 afc_corr[1:0] 5 ookfrzen 4 peakdeten 3 madeten 2:0 ookcnt[10] Register 2Dh. OOK Counter Value 2 Bit D7 D6 Name Type ...
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Register 2Eh. Slicer Peak Holder Bit D7 D6 Name Reserved Type w R/ Reset value = 00101110 Bit Name 7 Reserved 6:4 attack[2:0] 3:0 decay[3:0] Register 30h. Data Access Control Bit D7 D6 Name enpacrx lsbfrst w w Type R/ ...
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Register 31h. EZMAC ® Status Bit D7 D6 Name Reserved rxcrc1 Type R R Reset value = 00000000 Bit Name 7 Reserved 6 rxcrc1 5 pksrch 4 pkrx 3 pkvalid 2 crcerror 1:0 Reserved Tel: +86-755-82973805 D5 D4 pksrch pkrx ...
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Register 32h. Header Control 1 Bit D7 D6 Name bcen[3:0] Type Reset value = 00001100 Bit Name Broadcast Address (FFh) Check Enable enabled together with Header Byte Check then the header check the incoming ...
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Register 33h. Header Control 2 Bit D7 D6 Name Reserved Type R Reset value = 00100010 Bit Name 7 Reserved 6:4 hdlen[2:0] 3 fixpklen 2:1 synclen[1:0] 0 prealen[8] Tel: +86-755-82973805 hdlen[2:0] fixpklen Reserved. Header ...
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Register 34h. Preamble Length Bit D7 D6 Name Type Reset value = 00001000 Bit Name 7：0 prealen[7:0] Register 35h. Preamble Detection Control 1 Bit D7 D6 Name Type Reset value = 00101010 Bit Name 7：3 preath[4:0] 2:0 rssi_offset[2:0] Tel: +86-755-82973805 ...
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Register 36h. Synchronization Word 3 Bit D7 D6 Name Type Reset value = 00101101 Bit Name 7：0 sync[31:24] Register 37h. Synchronization Word 2 Bit D7 D6 Name Type Reset value = 11010100 Bit Name 7：0 sync[23:16] Register 38h. Synchronization Word ...
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Register 39h. Synchronization Word 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 sync[7:0] Register 3Eh. Packet Length Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 pklen[7:0] Check Header bytes 3 to ...
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Register 3Fh. Check Header 3 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 [31:24] chhd Register 40h. Check Header 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name chhd[23:16] 7：0 Register 3Ch. Transmit ...
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Register 42h. Check Header 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 chhd[7:0] Header Enable bytes control which bits of the Check Header bytes are checked against the corresponding bits in the ...
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Register 45h. Header Enable 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 hden [15:8] Register 46h. Header Enable 0 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 hden [7:0] Register 47h. ...
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Register 48h. Received Header 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name rxhd [23:16] 7：0 Register 49h. Received Header 1 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7：0 rxhd [15:8] Register 4Ah. ...
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Register 4Bh. Received Packet Length Bit D7 D6 Name Type Reset value = 11111111 Bit Name 7：0 rxplen[7:0] Register 4Fh. ADC8 Control Bit D7 D6 Name Reserved[7:6] Type R/W Reset value = 00000000 Bit Name 7：6 Reserved[7:6] 5:0 adc8[5:0] Tel: ...
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Register 50h. Analog Test Bus Select Bit D7 D6 Name Reserved Type R/W Reset value = 00000000 Bit Name 7:5 Reserved 4:0 atb[4:0] Tel: +86-755-82973805 D5 D4 Reserved. Analog Test Bus. The selection of internal analog testpoints that are muxed ...
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Table 32. Internal Analog Signals Available on the Analog Test Bus atb[4: ADC_ipoly10u 7 ADC_Refdac_p 8 ADC_ipoly10 9 ADC_Res1Ip 10 ADC_Res1Qp ...
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Register 51h. Digital Test Bus Select Bit D7 D6 Name Reserved ensctest Type R/W R/W Reset value = 00000000 Bit Name 7 Reserved 6 ensctest 5:0 dtb[5:0] Table 33. Internal Digital Signals Available on the Digital Test Bus Tel: +86-755-82973805 ...
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Table 33. Internal Digital Signals Available on the Digital Test Bus (Continued) Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com 112 ...
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The total settling time (cold start) of the PLL after the calibration can be calculated as T Register 53h. PLL Tune Time Bit D7 D6 Name Type Reset value = 01010010 Bit Name 7:3 pllts[4:0] 2:0 pllt0 Register 54h. PA ...
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Register 55h. Calibration Control Bit D7 D6 Name Reserved xtalstarthalf Type Reset value = x1x00100 Bit Name 7 Reserved 6 xtalstarthalf 5 adccaldone 4 enrcfcal 3 rccal 2 vcocaldp 1 vcocal 0 skipvco Tel: +86-755-82973805 D5 D4 ...
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Register 56h. Modem Test Bit D7 D6 Name bcrfbyp slicfbyp Type Reset value = 00000000 Bit Name 7 bcrfbyp 6 slicfbyp 5 dttype 4 oscdeten 3 ookth 2 refclksel 1 refclkinv 0 distogg Tel: +86-755-82973805 D5 ...
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Register 57h. Charge Pump Test Bit D7 D6 Name pfdrst fbdiv_rst Type Reset value = 00000000 Bit Name 7 pfdrst 6 fbdiv_rst 5 cpforceup 4 cpforcedn 3 cdonly 2:0 cdcurr[2:0] Register 58h. Charge Pump Current Trimming/Override ...
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Register 59h. Divider Current Trimming/Delta-Sigma Test Bit D7 D6 Name Reserved fbdivhc Type Reset value = 10000000 Bit Name 7 Reserved 6 fbdivhc 5:4 d3trim[1:0] 3:2 d2trim[1:0] 1:0 d1p5trim[1:0] Register 5Ah. VCO Current Trimming Bit D7 D6 ...
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Register 5Bh. VCO Calibration/Override Bit D7 Name vcocalov/vcdone Type w R/ Reset value = 00000000 Bit Name 7. vcocalov/vcdone 6:0 vcocal[6:0] Register 5Ch. Synthesizer Test Bit D7 D6 Name dsmdt vcotype Type Reset value = 0x001110 Bit ...
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Register 5Dh. Block Enable Override 1 Bit D7 D6 Name enmix enina Type R/W R/W Reset value = 00000000 Bit Name 7 Mixer Enable Override. enmix 6 enina LNA Enable Override. 5 enpga PGA Enable Override. 4 Reserved. Reserved 3 ...
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Register 5Fh. Block Enable Override 3 Bit D7 D6 Name enfrdv endv31 Type R/W R/W Reset value = 00000000 Bit Name 7 Fractional Divider Enable Override. enfrdv 6 endv31 Divider 3_1 Enable Override. 5 endv2 Divider 2 Enable Override. 4 ...
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Register 61h. Channel Filter Coefficient Value Bit D7 D6 Name Reserved Type R/W Reset value = 00000000 Bit Name 7:6 Reserved. Reserved Filter Coefficient Value in the Look-up Table Addressed by the 5:0 chfilval[5:0] chfiladd[3:0]. Register 62h. Crystal Oscillator/Power-on-Reset Control ...
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Register 63h. RC Oscillator Coarse Calibration/Override Bit D7 D6 Name rccov Type R/W Reset value = 00000000 Bit Name RC Oscillator Coarse Calibration Override. When rccov = 0 the internal Coarse Calibration results may be viewed by 7 rccov reading ...
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Register 65h. LDO Control Override Bit D7 D6 Name enspor enbias Type R/W R/W Reset value = 10000001 Bit Name 7 enspor 6 enbias 5 envcoldo 4 enifldo 3 enrfldo 2 enpllldo 1 endigldo 0 endigpwdn Register 66h. LDO Level ...
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Register 67h. Delta-Sigma ADC Tuning 1 Bit D7 D6 Name adcrst enrefdac Type R/W R/W Reset value = 00011101 Bit Name 7 adcrst 6 enrefdac 5 enadc 4 adctuneovr 3:0 adctune[3:0] Register 68h. Delta-Sigma ADC Tuning 2 Bit D7 D6 ...
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Register 69h. AGC Override 1 Bit D7 D6 Name Reserved Type R Reset value = 00100000 Bit Name 7:5 Reserved 4 agcen 3 lnagain 2:0 pga[3:0] Register 6Ah. AGC Override 2 Bit D7 D6 Name agcovpm agcslow Type R/W R/W ...
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Register 6Fh. TX Data Rate 0 Bit D7 D6 Name Type Reset value = 00111101 Bit Name Data Rate Lower Byte. 7:0 txdr[7:0] See formula above. Defaults = 40 kbps. Register 70h. Modulation Mode Control 1 Bit D7 D6 Name ...
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Register 71h. Modulation Mode Control 2 Bit D7 D6 Name Reserved Type R/W Reset value = 00000000 Bit Name 7:4 Reserved. Reserved 3 eninv RX Data. MSB of Frequency Deviation Setting, see "Register 72h. Frequency 2 fd[8] Deviation". 1:0 Reserved ...
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Register 72h. Frequency Deviation Bit D7 D6 Name Type Reset value = 00100000 Bit Name Frequency Deviation Setting. 7:0 fd[7:0] See formula above. Note: It's recommended to use modulation index higher (maximum allowable modulation index is 32). ...
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Register 74h. Frequency Offset 2 Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:2 Reserved Reserved. Upper Bits of the Frequency Offset Setting. fo[9] is the sign bit. The frequency offset can be calculated as Offset = ...
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Register 76h. Nominal Carrier Frequency Bit D7 D6 Name Type Reset value = 10111011 Bit Name Nominal Carrier Frequency Setting. 7:0 fc[15:8] See formula above. Register 77h. Nominal Carrier Frequency Bit D7 D6 Name Type Reset value = 10000000 Bit ...
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Register 79h. Frequency Hopping Channel Select Bit D7 D6 Name Type Reset value = 00000000 Bit Name 7:0 fhch[7:0] Frequency Hopping Channel Number. Register 7Ah. Frequency Hopping Step Size Bit D7 D6 Name Type Reset value = 00000000 Bit Name ...
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Register 7Bh. Turn Around and 15.4 Length Compliance Bit D7 D6 Name 15.4 Length Type R/W Reset value = 01111011 Bit Name 15.4 Packet Length Compliance. If set, then PK Length definition for both TX and RX will also include ...
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Register 7Fh. FIFO Access Bit D7 D6 Name Type Reset value = NA Bit Name FIFO Data. 7：0 fifod[7:0] A Read (R this address will begin a burst read of the RX FIFO. Tel: +86-755-82973805 D5 D4 ...
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... Serial Clock input. 0–V V digital input. This pin provides the serial data clock function for DD the 4-line serial data bus. Data is clocked into the RF31 on positive edge transitions. Serial Interface Select input. 0– function for the 4-line serial data bus. The signal is also used to signify burst read/write mode. ...
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... When SDN =1 the chip will be completely shutdown and the contents of the registers will be lost. The exposed metal paddle on the bottom of the RF31 supplies the RF and circuit ground(s) for the entire chip very important that a good solder connection is made between this exposed metal paddle and the ground plane of the PCB underlying the RF31 E-mail: sales@hoperf ...
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... Package Information Figure 34 illustrates the package details for the RF31, and Figure 35 illustrates the landing pattern details. Figure 35. QFN-20 Landing Pattern Dimensions Tel: +86-755-82973805 Figure 34. QFN-20 Package Dimensions Fax: +86-755-82973550 E-mail: sales@hoperf.com 136 http://www.hoperf.com ...
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Errata Status Summary Errata # Some non-standard frequencies are not 1 supported. Radio does not return to the low power state 2 when in Low Duty Cycle Mode. Additional tuning steps required for proper RX 3 mode operation. 4 ...
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Details 1. Description: Some non-standard frequencies are not supported. Impacts: Operation in frequencies between 240-280 MHz and 480-560 MHz should be avoided. Workaround: These are non-standard bands and should result in no customer impact; no workaround at this time. ...
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Description: Wake-up Timer and Low Duty Cycle Modes not functional. Impacts: These features are not supported. Workaround: Use the external microcontroller or the 32 kHz XTAL option on the RF22 to implement these functions. Resolution: Will be fixed in ...