CY2077 Cypress Semiconductor Corporation., CY2077 Datasheet

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CY2077

Manufacturer Part Number
CY2077
Description
High-accuracy Eprom Programmable Single-pll Clock Generator
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Cypress Semiconductor Corporation
Document Number: 38-07210 Rev. *C
Note
Logic Block Diagram
1. When using an external clock source, leave XTALOUT floating.
High-accuracy PLL with 12-bit multiplier and 10-bit
divider
EPROM programmability
3.3V or 5V operation
Operating frequency
Reference input from either a 10–30 MHz fundamental toned
crystal or a 1–75 MHz external clock
EPROM selectable TTL or CMOS duty cycle levels
Sixteen selectable post-divide options, using either PLL or
reference oscillator/external clock
Programmable PWR_DWN or OE pin, with asynchronous or
synchronous modes
Low jitter outputs typically
Controlled rise and fall times and output slew rate
Available in both commercial and industrial temperature ranges
Factory programmable device options
390 kHz–133 MHz at 5V
390 kHz–100 MHz at 3.3V
80 ps at 3.3V/5V
PWR_DWN
XTALOUT
external clock
XTALIN
or OE
or
[1]
ACCURACY
198 Champion Court
HIGH
PLL
Q
10 bits
High-accuracy EPROM Programmable
/ 1, 2, 4, 8, 16, 32, 64, 128
P
12 bits
Charge
Pump
Benefits
VCO
MUX
Enables synthesis of highly accurate and stable output clock
frequencies with zero PPM
Enables quick turnaround of custom frequencies
Supports industry standard design platforms
Services most PC, networking, and consumer applications
Lowers cost of oscillator as PLL can be programmed to a high
frequency using either a low-frequency, low-cost crystal, or an
existing system clock
Duty cycle centered at 1.5V or V
Provides flexibility to service most TTL or CMOS applications
Provides flexibility in output configurations and testing
Enables low-power operation or output enable function and
flexibility for system applications, through selectable instanta-
neous or synchronous change in outputs
Suitable for most PC, consumer, and networking applications
Has lower EMI than oscillators
Suitable to fit most applications
Easy customization and fast turnaround
Single-PLL Clock Generator
San Jose
Configuration
EPROM
,
CA 95134-1709
DD
Revised February 15, 2008
/2
CLKOUT
408-943-2600
CY2077
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CY2077 Summary of contents

Page 1

... Easy customization and fast turnaround Charge Pump Q 10 bits VCO P 12 bits HIGH ACCURACY PLL MUX / 16, 32, 64, 128 • 198 Champion Court • San Jose CY2077 /2 DD Configuration EPROM CLKOUT , CA 95134-1709 • 408-943-2600 Revised February 15, 2008 [+] Feedback [+] Feedback ...

Page 2

... CD-ROM drives, video CD players, DVD players, games, set-top boxes, and data/telecommunica- tions. CY2077 can generate a clock output up to 133 MHz 100 MHz at 3.3V. It has been designed to give the customer a very accurate and stable clock frequency with little to zero PPM error. ...

Page 3

... Power Management Features PWR_DWN and OE options are configurable by EPROM programming for the CY2077. In PWR_DWN mode, all active circuits are powered down when the control pin is set LOW. When the control pin is set back HIGH, both the PLL and oscil- lator circuit must relock. In the case of OE, the output is three-stated and weakly pulled down when the control pin is set LOW ...

Page 4

... 4.5 – 5.5V, output frequency <= 133 MHz 3.0 – 3.6V, output frequency <= 100 MHz 4.5 – 5. 3.0 – 3. 4.5 – 5.5V 4.5 – 5.5V 0. 5.0 DD CY2077 Min Typ Max Unit 0 2 0 – 0 – 0 2.4 V μA 10 μA ...

Page 5

... PWR_DWN pin LOW to output LOW [5] From power on OE pin LOW to output high-Z (T= period of output CLK) OE pin LOW to output high-Z OE pin LOW to HIGH (T= period of output CLK 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz 3.0V – 5.5V, Fo < 33 MHz DD CY2077 Min Typ Max Unit ...

Page 6

... 4.5 – 5.5V, output frequency <= 133 MHz 3.0 – 3.6V, output frequency <= 100 MHz 4.5 – 5. 3.0 – 3. 4.5 – 5.5V 4.5 – 5.5V 0. 5.0 DD CY2077 Min Max Unit 3.0 5.5 V –40 +85 ° MHz ...

Page 7

... 4.5V – 5.5V – 0. 4.5V – 5.5V – 0. 3.0V – 3.6V – 0. 3.0V – 3.6V [5] [5] = 3.0V – 3.6V, 4.5V – 5.5V, Fo > 33 MHz 3.0V – 5.5V, Fo < 33 MHz DD CY2077 Min Typ. Max 1 1 0.9 ...

Page 8

... In asynchronous mode, the power down or output three-state occurs within 25 ns regardless of position in the output clock cycle. Document Number: 38-07210 Rev. *C Figure 2. Duty Cycle Timing ( Figure 3. Output Rise/Fall Time VIH VIL t5a t5b Figure 5. Power up Timing t6 s VIH VIL High Impedance t7a High Impedance t7b CY2077 , 1/f 1/f 1 Page [+] Feedback [+] Feedback ...

Page 9

... Typical Rise/Fall Time [8] Trends for CY2077 Figure 7. Rise/Fall Time vs. VDD over Temperatures Rise Time vs. VDD -- CMOS duty Cycle Cload = 15pF 2.00 1.80 1.60 1.40 1.20 1.00 2.7 3.0 3.3 3.6 VDD (V) Rise Time vs. VDD -- TTL duty Cycle Cload = 15pF 0.70 0.60 0.50 0.40 0.30 0.20 4.0 4.5 5.0 5.5 VDD (V) Figure 8. Rise/Fall Time vs. Output Loads over Temperatures Rise Time vs. CLoad over Temperature VDD = 3 ...

Page 10

... Typical Duty Cycle [9] Trends for CY2077 Figure 9. Duty Cycle vs. V Duty Cycle vs. VDD over Temperature (TTL Duty Cycle Output, Fout=50MHz, Cload = 50pF) 55.00 53.00 51.00 49.00 47.00 45.00 4.0 4.5 5.0 5.5 VDD (V) Figure 11. Duty Cycle vs. Output Frequency over Temperatures Note 9. Duty cycle is measured at 1.4V for TTL output and 0.5 V Document Number: 38-07210 Rev. *C ...

Page 11

... Typical Jitter Trends for CY2077 Figure 12. Period Jitter (pk-pk) vs. V 100 Figure 13. Period Jitter (pk-pk) vs. Output Frequency over Temperatures 100 Document Number: 38-07210 Rev. *C over Temperatures DD Period Jitter (pk-pk) vs. VDD over Temperatures (Fout=40MHz, Cload = 30pF 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) Output Jitter (pk-pk) vs ...

Page 12

... The CY2077SC-xxx(T), CY2077SI-xxx(T), CY2077SXC-xxx(T), CY2077ZC-xxx(T), CY2077ZI-xxx(T) andCY2077ZXC-xxx(T), are factory programmed configurations. Factory programming is available for high-volume design opportunities. For more details, contact your local Cypress FAE or Cypress Sales Representative. 11. The CY2077F are field programmable. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document Number: 38-07210 Rev. *C CY2077 devices ...

Page 13

... REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] Z08.173 STANDARD PKG. ZZ08.173 LEAD FREE PKG. 0.25[0.010] 1.10[0.043] MAX. BSC GAUGE 0°-8° PLANE 0.076[0.003] SEATING PLANE CY2077 MAX. 0.010[0.254] X 45° 0.016[0.406] 0.0075[0.190] 0.0098[0.249] 51-85066 *C MAX. PART # 0.50[0.020] 0.09[[0.003] 0.70[0.027] 0.20[0.008] ...

Page 14

... Document History Page Document Title: CY2077 High-accuracy EPROM Programmable Single-PLL Clock Generator Document Number: 38-07210 REV. ECN NO. Issue Date ** 111727 02/07/02 *A 114938 07/24/02 *B 121843 12/14/02 *C 2104546 See ECN © Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

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