CY29351 Cypress Semiconductor Corporation., CY29351 Datasheet

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CY29351

Manufacturer Part Number
CY29351
Description
2.5v Or 3.3v, 200 Mhz, 9-output Zero Delay
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Cypress Semiconductor Corporation
Document Number: 38-07475 Rev. *B
Block Diagram
Output frequency range: 25 MHz to 200 MHz
Input frequency range: 25 MHz to 200 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2.5% max Output duty cycle variation
9 clock outputs: Drive up to 18 clock lines
Two reference clock inputs: LVPECL or LVCMOS
150-ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread Aware™
Output enable/disable
Pin-compatible with MPC9351
Industrial temperature range: –40°C to +85°C
32-pin 1.0-mm TQFP package
PLL_EN
PECL_CLK
REF_SEL
SELA
FB_IN
SELB
SELC
SELD
TCLK
OE#
PRELIMINARY
198 Champion Court
Detector
Phase
LPF
500 MHz
VCO
200 -
Functional Description
The CY29351 is a low voltage high performance 200 MHz
PLL-based zero delay buffer designed for high speed clock distri-
bution applications.
The CY29351 features LVPECL and LVCMOS reference clock
inputs and provides 9 outputs partitioned in four banks of one,
one, two, and five outputs. Bank A divides the VCO output by two
or four while the other banks divide by four or eight per SEL(A:D)
settings
allow output to input ratios of 4:1, 2:1, 1:1, 1:2, and 1:4. Each
LVCMOS compatible output can drive 50Ω series or parallel
terminated transmission lines. For series terminated trans-
mission lines, each output can drive one or two traces giving the
device an effective fanout of 1:18.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range of
output frequencies from 25 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
one of the outputs. The internal VCO is running at multiples of
the input reference clock set by the feedback divider
“Frequency Table,”
When PLL_EN# is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
(Table 3, “Function Table,”
÷2 / ÷4
÷4 / ÷8
÷4 / ÷8
÷4 / ÷8
San Jose
2.5V or 3.3V, 200 MHz,
on page 3).
9-Output Zero Delay
,
CA 95134-1709
QA
QB
QC0
QC1
QD0
QD1
QD2
QD3
QD4
on page 3). These dividers
Revised January 21, 2008
CY29351
408-943-2600
(Table 2,
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CY29351 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document Number: 38-07475 Rev. *B PRELIMINARY Functional Description The CY29351 is a low voltage high performance 200 MHz PLL-based zero delay buffer designed for high speed clock distri- bution applications. The CY29351 features LVPECL and LVCMOS reference clock inputs and provides 9 outputs partitioned in four banks of one, one, two, and five outputs ...

Page 2

... VDD 2.5V or 3.3V power supply for PLL VDD 2.5V or 3.3V power supply for core, inputs, and bank A output clock Ground Analog ground Ground Common ground . Alternatively, each output drives up to two 50 Ω series terminated transmission TT CY29351 Description [2,3] [2,3] [2,3] [5,6] [2,3] range and the input swing CMR Page ...

Page 3

... D) Condition Functional Relative Relative Functional Ripple frequency < 100 kHz Non Functional Functional Functional Functional Functional Manufacturing test CY29351 Input Frequency Range (AVDD = 2.5V) 100 MHz to 190 MHz 50 MHz to 95 MHz 25 MHz to 47.5 MHz 1 Min Max Unit –0.3 5.5 V 2.375 3.465 V – ...

Page 4

... LVPECL LVPECL – AVDD only All VDD pins except AVDD Outputs loaded at 100 MHz Outputs loaded at 200 MHz CY29351 Min Typ. Max Unit – – 0.7 V 1.7 – 250 – 1000 mV 1.0 – V – 0.6 ...

Page 5

... Same frequency Multiple frequencies Same frequency Multiple frequencies . Parameters are guaranteed by characterization and are not 100% tested impacts static phase offset t(φ). PP CY29351 Min Typ. Max Unit 200 – 380 MHz 100 – 190 ...

Page 6

... TCLK to FB_IN, same VDD PCLK to FB_IN, same VDD Banks at same voltage Banks at different voltages ÷2 feedback ÷4 feedback ÷8 feedback Same frequency Multiple frequencies Same frequency Multiple frequencies IO same V DD CY29351 Min Typ. Max Unit 200 – 500 MHz 100 – 200 MHz 50 – ...

Page 7

... t(φ) FB_IN t(φ) CY29351 = 3. 3. ...

Page 8

... Figure 6. Output Duty Cycle (DC) VDD VDD GND 100% Figure 7. Output-to-Output Skew, t sk(O) t SK(O) Package Type CY29351 VDD VDD/2 GND VDD VDD/2 GND Product Flow Industrial, –40°C to 85°C Industrial, –40°C to 85°C Page [+] Feedback [+] Feedback ...

Page 9

... Package Drawing and Dimension Figure 8. 32-Pin Thin Plastic Quad Flatpack 1.0 mm Document Number: 38-07475 Rev. *B PRELIMINARY CY29351 51-85063-*B Page [+] Feedback [+] Feedback ...

Page 10

... Document History Page Document Title: CY29351 2.5V or 3.3V, 200 MHz, 9-Output Zero Delay Buffer Document Number: 38-0747 REV. ECN No. Issue Date Orig. of Change ** 128152 07/07/03 *A 245448 See ECN *B 2001108 See ECN PYG/KVM/AESA © Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

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