SSD2119 Crystalfontz America, Inc.,, SSD2119 Datasheet - Page 29

• Manufacturer Part Number: SSD2119
• Description: 320 Rgb X 240 Tft Lcd Driver Integrated Power Circuit, Source And Gate Driver And Ram
• Manufacturer: Crystalfontz America, Inc.,

7
7.1
7.1.1
7.1.2
SSD2119
The System Interface unit consists of three functional blocks for driving the 6800-series parallel interface,
8080-series high speed parallel interface, 3-lines serial peripheral interface and 4-lines serial peripheral
interface. The selection of different interface is done by PS3, PS2, PS1 and PS0 pins. Please refer to the
pin descriptions on page 13 and 13.
FUNCTION BLOCK DESCRIPTIONS
Data Read
Data Write
Command Read
Command Write
System Interface
MPU Parallel 6800-series Interface
The parallel Interface consists of 18 bi-directional data pins D[17:0], RW, DC, E and CS.
RW input high indicates a read operation from the Graphical Display Data RAM (GDDRAM) or
status register. RW input low indicates a write operation to Display Data RAM or Internal Command
Registers depending on the status of DC input.
The E input served as data latch signal (clock) when high provided that CS is low. Please refer to
Parallel Interface Timing Diagram of 6800-series microprocessors.
In order to match the operating frequency of the GDDRAM with that of the MCU, pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual
display data read. This is shown in the following diagram.
MPU Parallel 8080-series Interface
The parallel interface consists of 18 bi-directional data pins D[17:0], WR, DC, and CS.
RD input served as data read latch signal (clock) when low provided that CS is low. Weather reading
the display data from GDDRAM or reading the status from the status register is controlled by DC.
WR input served as data write latch signal (clock) when low provided that CS is low. Weather writing
the display data to the GDDRAM or writing the command to the command register is controlled by
DC. A dummy read is also required before the first actual display data read for 8080-series interface.
Please refer to .
DATA BUS
RW#(WR#)
E
Rev 1.4
write column address
P 29/95
N
6800 – series Parallel
18/16/9/8-bits
18/16/9/8-bits
Status only
Interface
Table 7-1: Data bus selection modes
Jun 2009
Yes
Figure 7-1: Read Display Data
dummy read
8080 – series Parallel
18/16/9/8-bits
18/16/9/8-bits
data read1
Status only
Interface
n
Yes
data read 2
n+1
MCU Serial Interface
8-bits
8-bits
Yes
No
data read 3
n+2
Solomon Systech