STFPC320 STMicroelectronics, STFPC320 Datasheet - Page 19

• Manufacturer Part Number: STFPC320
• Description: Front Panel Controller/driver With Standby Power Management And Real-time Clock
• Manufacturer: STMicroelectronics

STFPC320
6
6.1
6.2
Real Time Clock (RTC) operation
Real-time clock
The RTC operates as a slave device through the slave address of the STFPC320 on the
serial bus. Access is obtained by implementing a start condition followed by the correct
slave address (Write: 0x52H and Read: 0x53H). The 16 bytes contained in the device can
then be accessed sequentially in the following order:
1. Reserved
2. Seconds Register
3. Minutes Register
4. Hours Register
5. Square Wave/Day Register
6. Date Register
7. Century/Month Register
8. Year Register
9. Calibration Register
10. Watchdog Register
11 - 15. Alarm Registers
16. Flags Register
2-Wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage (typical voltage is 3.3V) via a pull-up resistor (typical
value is 10K). The following protocol has been defined:
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Accordingly, the following bus conditions have been defined:
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Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is High.
Changes in the data line, while the clock line is High, will be interpreted as control
signals.
Bus not busy: Both data and clock lines remain High.
Start data transfer: A change in the state of the data line, from high to Low, while the
clock is High, defines the START condition.
Stop data transfer: A change in the state of the data line, from Low to High, while the
clock is High, defines the STOP condition.
Data Valid: The state of the data line represents valid data when after a start condition,
the data line is stable for the duration of the high period of the clock signal. The data on
the line may be changed during the Low period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop
Real Time Clock (RTC) operation
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