BU9832GUL-W ROHM Co. Ltd., BU9832GUL-W Datasheet - Page 7

• Manufacturer Part Number: BU9832GUL-W
• Description: 1,024?8 Bit Electrically Erasable Prom
• Manufacturer: ROHM Co. Ltd.

◇Functional Description
○Status Register
○WP pin
○HOLD pin
to be high to enable WP pin function.
The device has status register.
Status register consists of 8bits and is shown following parameters.
3bits(WPEN, BP0 and BP1) are set by “Write Status Register” commands, which are non-volatile.
Specification of endurance and data retention are as well as memory array.
WEN bit is set by “Write enable” and “Write Disable” commands. After power become on, the device is disable
status register by “Read Status Register” command input.
mode. R/B bit is a read-only and status bit. The device is clocked out value of the
The device inhibits to write the data into status register during WP is low. WPEN bit in status register needs
After HOLD pin is brought high to release hold state during SCK is low, the device resumes to transfer the data.
For example, in case the device is hold state after A5 (the address data) input in read command, to resume the
data transmission enable starting A4 (the address data) input
after hold state is release. When CS is brought high with hold state, the device is reset and cannot resume the
data transmission.
HOLD pin is able to suspend data transmission for a time (Hold state). HOLD pin is normally high for
transmission of the data. SCK and SI input are “Don’t Care” and SO output state is
Hi-Z for hold state.
WPEN
BP0/BP1
WEN
R/B
WPEN
Bit7
Bit
Bit6
0
BP1
0
0
1
1
WP pin ENABLE Bit
WPEN=0 ： no use
Block write protection for memory array
（EEPROM）
Write enable/disable state bit
READY／BUSY status bit
Bit5
0
WEN=1 ： write enable
WEN=0 ： write disable
R/B=0 ： READY
R/B=1 ： BUSY
BP0
Table2. Block Write Protection
Table1. Status Register
Bit4
0
1
0
1
0
WPEN=1
REV. B
Block Write Protection
Bit3
BP1
Definition
300h-3FFh
200h-3FFh
000h-3FFh
None
Protect
Bit2
BP0
WEN
Bit1
×:Don't care
Bit0
R/B
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