IXXBB1 Fujitsu Microelectronics, Inc., IXXBB1 Datasheet - Page 56

• Manufacturer Part Number: IXXBB1
• Description: 32-bit Proprietary Microcontroller Cmos Fr60 Mb91301 Series
• Manufacturer: Fujitsu Microelectronics, Inc.

56
MB91301 Series
1. External Bus Interface Controller
External Bus Interface Controller Features
PERIPHERAL RESOURCES
• Maximum output address width = 32-bit (4 Gbytes memory space)
• Various different types of external memory (8-bit, 16-bit, or 32-bit devices) can be directly connected and the
• Memory can be divided into eight independent banks (chip select areas) with a separate chip select output
• The following functions can be set independently for each chip select area :
• Different detailed timing settings can be set for each timing type
• DMA supports fly-by transfer
• Supports external bus arbitration using BRQ and BGRNT.
• Pins not used by the external interface can be set as general purpose I/O ports.
controller can support multiple devices with different access timings.
Asynchronous SRAM, asynchronous ROM/FLASH memory (supports multiple write strobe access or byte-
enable access)
Page mode ROM/FLASH memory (2, 4, or 8 page size)
Burst mode ROM/FLASH memory
Address/data multiplexed bus (8-bit or 16-bit width only)
Synchronous memory (built-in ASIC memory, etc.)
Note:
for each bank.
The size of each area can be set in 64 Kbytes increments (the size of each chip select area can range from
64 Kbytes to 2 Gbytes)
Each area can be located anywhere in the physical address space (subject to boundary limitations based on
the area size)
Chip select area enable/disable (Access is not performed to disabled areas)
Setting of an access timing type to support each type of memory (For SDRAM, only the CS6 and CS7 areas
can be connected.)
Detailed access timing settings (wait cycles and similar settings for each access type)
Data bus width (8-bit, 16-bit, 32-bit)
Byte-ordering setting (big or little endian)
Note:
Write-prohibit setting (read-only areas)
Enable or disable loading into built-in cache
Enable or disable prefetch function
Maximum burst length setting (1, 2, 4, 8)
Even for the same type, different settings can be used for each chip select area.
Up to 15 auto-wait cycles can be specified. (For asynchronous SRAM, ROM, Flash, and I/O areas)
The bus cycle can be extended by the external RDY input. (For asynchronous SRAM, ROM, Flash, and I/O
areas)
Fast access wait and page wait settings are supported (For burst/page mode ROM and Flash areas)
Idle cycles, recovery cycles, setup delays, and similar can be inserted.
Capable of setting timing values such as the CAS latency and RAS-CAS delay (SDRAM area)
Capable of controlling the distributed/centralized auto-refresh, self-refresh, and other refresh timings (SDRAM
area)
Transfer between memory and I/O can be performed by a single access.
Memory wait cycles can be synchronized with the I/O wait period during fly-by transfer.
Hold times can be maintained by extending access to the data source only.
Separate idle and recovery cycle settings can be specified for use in fly-by transfer.
Synchronous SRAM cannot be directly connected.
The CS0 area must be big endian.