ADN2807 Analog Devices, Inc., ADN2807 Datasheet - Page 6

• Manufacturer Part Number: ADN2807
• Description: 155/622 Mb/s Clock And Data Recovery Ic With Integrated Limiting Amp
• Manufacturer: Analog Devices, Inc.

ADN2807
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions
Pin No.
1
2, 26, 28, Pad
3, 9, 16, 19,
22, 27, 29, 33,
34, 42, 43, 46
4
5
6
7
8
10
11
12
13
14
15
17
18
20, 47
21
23
24
25
30
31
32
35, 36
37
38
39
40
41
44
45
48
1
Type: P = Power, AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output
Mnemonic
THRADJ
VCC
VEE
VREF
PIN
NIN
SLICEP
SLICEN
LOL
XO1
XO2
REFCLKN
REFCLKP
REFSEL
TDINP
TDINN
VCC
CF1
REFSEL1
REFSEL0
CF2
SEL1
NC
SEL0
VCC
DATAOUTN
DATAOUTP
SQUELCH
CLKOUTN
CLKOUTP
BYPASS
SDOUT
LOOPEN
Type
AI
P
P
AO
AI
AI
AI
AI
DO
AO
AO
DI
DI
DI
AI
AI
P
AO
DI
DI
AO
DI
DI
P
DO
DO
DI
DO
DO
DI
DO
DI
1
Description
LOS Threshold Setting Resistor.
Analog Supply.
Ground.
Internal VREF Voltage. Decouple to GND with a 0.1 µF capacitor.
Differential Data Input.
Differential Data Input.
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Loss-of-Lock Indicator. LVTTL active high.
Crystal Oscillator.
Crystal Oscillator.
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Differential REFCLK Input. LVTTL, LVCMOS, LVPECL, LVDS (LVPECL, LVDS only at 155.52 MHz).
Reference Source Select. 0 = on-chip oscillator with external crystal. 1 = external clock source, LVTTL.
Differential Test Data Input. CML.
Differential Test Data Input. CML.
Digital Supply.
Frequency Loop Capacitor.
Reference Frequency Select (See Table 6) LVTTL.
Reference Frequency Select (See Table 6) LVTTL.
Frequency Loop Capacitor.
Data Rate Select (See Table 5) LVTTL.
No Connect.
Data Rate Select (See Table 5) LVTTL.
Output Driver Supply.
Differential Retimed Data Output. CML.
Differential Retimed Data Output. CML.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Clock Output. CML.
Differential Recovered Clock Output. CML.
Bypass CDR Mode. Active high. LVTTL.
Loss-of-Signal Detect Output. Active high. LVTTL.
Enable Test Data Inputs. Active high. LVTTL.
THRADJ 1
SLICEN 8
SLICEP 7
VREF 4
VCC 2
VEE 3
VEE 9
LOL 10
XO1 11
XO2 12
NIN 6
PIN 5
Figure 2. Pin Configuration
Rev. A | Page 6 of 20
PIN 1
INDICATOR
ADN2807
TOPVIEW
36 VCC
35 VCC
34 VEE
33 VEE
32 SEL0
31 NC
30 SEL1
29 VEE
28 VCC
27 VEE
26 VCC
25 CF2