ADN2807 Analog Devices, Inc., ADN2807 Datasheet - Page 9

• Manufacturer Part Number: ADN2807
• Description: 155/622 Mb/s Clock And Data Recovery Ic With Integrated Limiting Amp
• Manufacturer: Analog Devices, Inc.

LOS RESPONSE TIME
The LOS response time is the delay between the removal of the
input signal and indication of loss of signal (LOS) at SDOUT.
The ADN2807’s response time is 300 ns typ when the inputs are
dc-coupled. In practice, the time constant of ac coupling at the
quantizer input determines the LOS response time.
JITTER SPECIFICATIONS
The ADN2807 CDR is designed to achieve the best bit-error-
rate (BER) performance, and has exceeded the jitter transfer,
generation, and tolerance specifications proposed for
SONET/SDH equipment defined in the Telcordia Technologies
specification. Jitter is the dynamic displacement of digital signal
edges from their long-term average positions measured in UI
(unit intervals), where 1 UI = 1 bit period. Jitter on the input
data can cause dynamic phase errors on the recovered clock
sampling edge. Jitter on the recovered clock causes jitter on the
retimed data. The following sections briefly summarize the
specifications of the jitter generation, transfer, and tolerance in
accordance with the Telcordia document (GR-253-CORE, Issue
3, September 2000) for the optical interface at the equipment
level, and the ADN2807 performance with respect to those
specifications.
Jitter Generation
The jitter generation specification limits the amount of jitter
that can be generated by the device with no jitter and wander
applied at the input.
Jitter Transfer
The jitter transfer function is the ratio of the jitter on the output
signal to the jitter applied on the input signal versus the
frequency. This parameter measures the limited amount of jitter
on an input signal that can be transferred to the output signal
(Figure 11).
Table 4. Jitter Transfer and Tolerance: SONET Specifications vs. ADN2807
Rate
OC-12
OC-3
2
Jitter tolerance measurements are limited by test equipment capabilities.
SONET
Spec (f
500 kHz
130 kHz
C
)
ADN2807
(kHz)
140
48
Jitter Transfer
Implementation
Margin
3.6
2.7
Mask Corner
Frequency (kHz)
250 kHz
65 kHz
Rev. A | Page 9 of 20
Jitter Tolerance
The jitter tolerance is defined as the peak-to-peak amplitude of
the sinusoidal jitter applied on the input signal that causes a
1 dB power penalty. This is a stress test intended to ensure that
no additional penalty is incurred under the operating
conditions (Figure 12).
0.1
ADN2807
4.8 MHz
600 kHz
0.15
1.5
15
ACCEPTABLE
RANGE
f
0
Jitter Tolerance
Figure 12. SONET Jitter Tolerance Mask
SONET Spec
(UI p-p)
0.15
0.15
Figure 11. Jitter Transfer Curve
JITTER FREQUENCY (kHz)
JITTER FREQUENCY (Hz)
f
f
1
C
ADN2807
(UI p-p)
1.0
1.0
f
SLOPE = –20dB/DECADE
2
f
3
SLOPE = –20dB/DECADE
Implementation
Margin
6.67
6.67
ADN2807
f
4
2