ADN2865 Analog Devices, Inc., ADN2865 Datasheet - Page 11

• Manufacturer Part Number: ADN2865
• Description: Continuous Rate 12.3mb/s To 2.7gb/s Clock And Data Recovery Ic W/loop Timed Serdes
• Manufacturer: Analog Devices, Inc.

Preliminary Technical Data
Table 5. Pin Function Descriptions
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Pin #
SDOUT
RXDATN1
RXDATP1
RXDATN0
RXDATP0
VCC3
VCC7
SERDATN
SERDATP
SERCLKN
SERCLKP
TXDAT7
TXDAT6
TXDAT5
TXDAT4
TXCLK
TXDAT3
TXDAT2
TXDAT1
TXDAT0
VREG
CF1
VEE2
VCC2
VEE4
VCC4
REFN
REFP
THRADJ
LOL
VEE1
SLICEN
SLICEP
NIN
PIN
VREF
VCC1
SCK
VCC6
SDA
RXCLKN
RXCLKP
RXDATN7
RXDATP7
VCC5
RXDATN6
RXDATP6
RXDATN5
RXDATP5
VCC5
RXDATN4
RXDATP4
RXDATN3
RXDATP3
RXDATN2
RXDATP2
Mnemonic
DO
DO
DO
DO
DO
PWR
PWR
DO
DO
DO
DO
DI
DI
DI
DI
DI
DI
DI
DI
DI
AO
AO
PWR
PWR
PWR
PWR
DI
DI
AO
DO
PWR
AI
AI
AI
AI
AO
PWR
DI
PWR
DI
DO
DO
DO
DO
PWR
DO
DO
DO
DO
PWR
DO
DO
DO
DO
DO
DO
Type
Active high, Loss of signal indicator. (LVTTL)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output.
Differential receive data output.
Power for CDR & Serialiser
Power for CML drivers
Differential serialized data output to LDD. (CML)
Differential serialized data output to LDD. (CML)
Differential clock for serialized Tx data. (CML)
Differential clock for serialized Tx data. (CML)
Transmit data input.
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Qualifying clock for transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input. (LVTTL)
Transmit data input.
Decoupling node for VCO power.
PLL loop filter capacitor.
Ground for VCO / PLL / Gm
Power for VCO / PLL / Gm
Ground for FLL
Power for FLL
Reference clock input. (LVDS/LVTTL)
Reference clock input. (LVDS/LVTTL)
LOS Threshold Setting Resistor.
Active high, Loss-of-Lock Indicator. (LVTTL)
Ground for Limamp / LOS
Differential Slice Level Adjust Input.
Differential Slice Level Adjust Input.
Differential serial input to Limiting Amp. (CML)
Differential serial input to Limiting Amp. (CML)
Decoupling node for internal voltage reference.
Power for Limamp / LOS
I2C Serial Clock Input.
Power for Deserialiser, LVDS pre-drivers
I2C Serial Data Input.
Qualifying clock for Rx Data Outputs. (LVDS)
Qualifying clock for Rx Data Outputs. (LVDS)
Differential receive data output.
Differential receive data output.
Power for LVDS drivers
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Power for LVDS Drivers
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
Differential receive data output. (LVDS)
First bit sent.
Last bit
Rev. PrA | Page 11 of 33
sent.
Last bit received.
Last bit received.
Last bit received.
Last bit received.
(LVTTL)
(LVTTL)
Description
(LVDS)
(LVDS)
(LVDS)
(LVDS)
ADN2865