LTC2753-14 Linear Technology Corporation, LTC2753-14 Datasheet
LTC2753-14
Related parts for LTC2753-14
LTC2753-14 Summary of contents
Page 1
... DACs offer six output ranges—two unipolar and four bipolar—that can be programmed through the parallel interface, or pinstrapped for operation in a single range. The LTC2753 DACs use a bidirectional input/output parallel interface that allows readback of any on-chip register. A power-on reset circuit resets the DAC outputs to 0V when power is initially applied ...
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... LTC2753-14 UK PACKAGE 48-LEAD (7mm × 7mm) PLASTIC QFN T = 125°C, θ = 29°C/W JMAX JA EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB PART MARKING* PACKAGE DESCRIPTION LTC2753UK-12 48-Lead (7mm × 7mm) Plastic QFN LTC2753UK-12 48-Lead (7mm × ...
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... Output Settling Time Glitch Impulse Digital-to-Analog Glitch Impulse Multiplying Feedthrough Error THD Total Harmonic Distortion Output Noise Voltage Density unless otherwise specifi ed. The DD REF LTC2753-12 LTC2753-14 MIN TYP MAX MIN TYP MAX ● ● ● ...
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... LTC2753 ELECTRICAL CHARACTERISTICS specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T SYMBOL PARAMETER Power Supply V Supply Voltage DD I Supply Current Digital Inputs V Digital Input High Voltage IH V Digital Input Low Voltage ...
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... CONDITIONS C = 10pF L (Note 10) No Update No Update (Note 10) (Note 10) (Note 10) No Data Shoot-Through (Note 10) (Note 10 10pF L (Note 10 10pF L (Note 10) No Update No Update LTC2753 MIN TYP MAX UNITS ● ● ● ● ● ● ● ...
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... LTC2753 TIMING CHARACTERISTICS otherwise specifi cations are 25°C. A SYMBOL PARAMETER V = 2. READ Falling Edge to UPD Rising Edge 22 t I/O Bus Hi-Z to Read Rising Edge 23 t Read Falling Edge to I/O Bus Active 24 CLR Timing CLR Pulse Width Low t 25 Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device ...
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... DNL 0.8 ±5V RANGE 0.6 0.4 +INL 0.2 0.0 –INL –0.2 –0.4 –0.6 –0.8 –1 –10 –8 (V) 2753 G08 LTC2753 T = 25°C, unless otherwise noted. A INL vs Temperature 1 0 REF ±10V RANGE 0.6 0.4 +INL 0.2 0.0 –INL –0.2 –0.4 –0.6 –0.8 –1.0 65535 –40 – ...
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... LTC2753 TYPICAL PERFORMANCE CHARACTERISTICS LTC2753-16 INL 1.0 0.8 0.6 0.4 +INL 0.2 0.0 –INL –0.2 –0.4 –0.6 –0.8 –1.0 2.5 3 3.5 4 4.5 5 5.5 V (V) DD 2751 G09b LTC2753-14 Integral Nonlinearity (INL REF ±10V RANGE 0.6 0.4 0.2 0.0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 CODE LTC2753-12 Integral Nonlinearity (INL) 1 ...
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... TYPICAL PERFORMANCE CHARACTERISTICS LTC2753-12, LTC2753-14, LTC2753-16 Midscale Glitch UPD 5V/DIV V OUT 2mV/DIV 500ns/DIV USING AN LT1469 REF FEEDBACK RANGE Logic Threshold vs Supply Voltage 2 1.75 1.5 RISING 1.25 FALLING 1 0.75 0.5 2 Supply Current vs Logic Input Voltage 20 15 1nV•S (TYP 2753 G15 ...
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... D0-D6 (Pins 22-28): LTC2753-16 Only. DAC Input/Output Data Bits. These I/O pins set and read back the DAC code the LSB. NC (Pins 25-30): LTC2753-12 Only. No Internal Connection. NC (Pins 27-30): LTC2753-14 Only. No Internal Connection. NC (Pins 29, 30): LTC2753-16 Only. No Internal Con- nection. GND (Pin 31): Shield Ground, provides necessary shielding for I ...
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... Typical Applications). Typically –5V; accepts up to ±15V. The impedance looking into this pin is 10k to ground (R Exposed Pad (Pin 49): Ground. The Exposed Pad must be soldered to the PCB. LTC2753 to ground. VOSB to ground. VOSA fl ows through the feedback resistor (Pin 2) ...
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... LTC2753 BLOCK DIAGRAM 16 DATA I /O I/O 6-14, 22-28 PORT SPAN I/O 3, 38, 33 PORT 17 A1 DAC ADDRESS REFA R IN COM DATA INPUT 16 DATA DAC 16 REGISTER REGISTER SPAN INPUT 3 SPAN DAC 3 REGISTER REGISTER 16 16 DATA INPUT DATA DAC REGISTER REGISTER SPAN INPUT ...
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... Write, Update and Clear Timing VALID VALID VALID Readback Timing VALID VALID VALID LTC2753 VALID t 25 2753 TD01 VALID 2753 TD02 2753f 13 ...
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... CLR resets all data registers, while leaving the span registers undisturbed DAC A MSPAN DAC B D/S WR UPD READ A1 A0 Figure 1. Using MSPAN to Confi gure the LTC2753 for Single-Span Operation (±10V Range). LTC2753-16 2753 F01 16 DATA I/O 2753f ...
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... I/O ports. The I/O pins are grouped into two ports: data and span. The data I/O port comprises pins D0-D11, D0-D13 or D0-D15 (LTC2753-12, LTC2753-14 or LTC2753-16, respectively). The span I/O port comprises pins S0, S1 and S2 for all parts. Each DAC channel has a set of data registers that are controlled and read back from the data I/O port ...
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... Codes not shown are reserved and should not be used. Table 3. Address Codes DAC CHANNEL A VOSX B ALL* Codes not shown are reserved and should not be used. *If readback is taken using the All DACs address, the LTC2753 defaults to . OUT2 DAC A. SPAN Unipolar Unipolar 0V to 10V Bipolar – Bipolar – ...
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... INPUT HI-Z DATA I/O OUTPUT UPD D/S READ 010 8000 011 C000 H = 2.5V) using readback to check the contents of the input OUT HI-Z H 8000 H INPUT REGISTER DAC REGISTER LTC2753 H UPDATE (±5V RANGE 0V) OUT 2753 TD03 4000 H UPDATE (5V) UPDATE (–5V) 2753 TD04 0000 H UPDATE (2.5V) 2753 TD05 2753f 17 ...
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... LTC2753-14 and the LTC2753-12. However, the results obtained from Tables 4 and 5 are in 16-bit LSBs. Divide these results by 4 (LTC2753-14) and 16 (LTC2753-12) to obtain the correct LSB sizing. Table 6 contains a partial list of LTC precision op amps recommended for use with the LTC2753. The easy-to-use ...
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... DAC settling time and op amp selection. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifi er for use with the LTC2753 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2753 is directly affected by the voltage reference ...
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... When the resistance of this circuit board trace becomes greater than 1Ω, a force/sense am- must be tied OUT2 plifi er confi guration should be used to drive this pin (see Figure 2). This preserves the excellent accuracy (1LSB INL and DNL) of the LTC2753-16. 2753f ...
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... OUT2 1 2 *SCHOTTKY BARRIER DIODE LTC2753- OFSA 46 R FBA OUT1A R 1 COM DAC OUT2A REFA VOSA 2753 F02 from GND with a Force/Sense Amplifi er. OUT2 LTC2753 2 – LT1001 3 + ZETEX* BAT54S 3 15pF 2 – 1/2 LT1469 OUTA 3 + 2753f 21 ...
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... LTC2753 TYPICAL APPLICATIONS Dual 16-Bit V V REF 1/2 LT1469 2 – 150pF 22 DAC with Software-Selectable Ranges OUT LTC2753- OFSA COM DAC A R2 C1* REFA 48 REFB 39 DAC OFSB 16 DATA I/O I/O PORT D15 - D0 3 SPAN I/O I/O PORT UPD READ D/S CLR MSPAN ...
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... Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704 Rev C) 0.70 ±0.05 5.50 REF 6.10 ±0.05 7.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.75 ± 0. 0.115 R = 0.10 TYP 5.15 ± 0.10 5.50 REF (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2753 TYP 47 48 0.40 ± 0. PIN 1 CHAMFER C = 0.35 5.15 ± 0.10 (UK48) QFN 0406 REV C 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 23 ...
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... D15 REFA REFB DD OFSA OFSB IN COM 7 D14 8 D13 9 D12 D11 D10 LTC2753- D/S WR CLR READ UPD MSPAN GND GND D/S WR CLR READ UPD COMMENTS 1ppm/°C Maximum Drift 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise 90MHz GBW, 22V/μ ...