MG74K Oki Semiconductor, MG74K Datasheet
MG74K
Related parts for MG74K
MG74K Summary of contents
Page 1
... D S ATA HEET 0.15µm Customer Structured Arrays MG74K/75K/76K March 2003 T S ...
Page 2
... CONTENTS Description ................................................................................................................................................................1 Features .....................................................................................................................................................................1 MG74K/75K/76K Family Listing ......................................................................................................................... 2 Array Architecture ................................................................................................................................................... 3 MG74K/75K/76K CSA Layout Methodology ..............................................................................................4 Electrical Characteristics ......................................................................................................................................... 6 Macro Library ......................................................................................................................................................... 10 Macrocells for Driving Clock Trees ............................................................................................................... 11 OKI Advanced Design Center Cad Tools ........................................................................................................... 12 Design Process........................................................................................................................................................ 13 Automatic Test Pattern Generation ...
Page 3
... The 0.15µm CSA family operates using 1.5V VDD core with optimized 3.3V I/O and 5V tolerant I/O buffers. The 4-, 5-, and 6-layer metal MG74K/75K/76K series contains 21 base arrays, offering up to 868 I/O pads and over 25M raw gates. These CSA sizes are designed to fit the most popular quad flat pack (QFP), low profile QFPs (LQFPs), thin QFPs (TQFPs), thin fine pitch land grid array (TFLGAs), low pro- file fine pitch ball grid array (LFBGAs), and plastic ball grid array (PBGA) packages ...
Page 4
... MG74K/75K/76K FAMILY LISTING CSA Base No ...
Page 5
... ARRAY ARCHITECTURE The primary components of a 0.15µm MG74K/75K/76K circuit include: • I/O base cells • ...
Page 6
... MG74K/75K/76K CSA Layout Methodology The procedure to design, place, and route a CSA is as follows ...
Page 7
... Figure 3 marks the area in which placement and routing is performed with cross hatching. Figure 3. Random Logic Place and Route MG74K/75K/76K Oki Semiconductor 5 ...
Page 8
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 9
... V (50k pull-down) OH DDIO (50k pull-up DDIO 3.3V, and T = 25° typical process. DDIO j MG74K/75K/76K = -40 to +85° Rated Value [1] Min. Typ. Max. 2.0 – 0.3 DDIO 2.0 – 5.5 -0.3 – 0.8 -0.3 – 0.8 – – 2.1 0.7 – ...
Page 10
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 11
... V, and for a typical process. DDIO j MG74K/75K/76K = 25°C) j [1] [2] [3] Conditions Rated Value 0.038 0.034 0.027 F 0.047 0.038 0.033 0.231 0.168 0.097 F standard wire length 0.280 ...
Page 12
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 13
... Satisfy the maximum load and maximum transition delay constraints. 2. Satisfy the maximum delay constraint. 3. Satisfy the maximum skew constraint. 4. Minimize the size of the clock tree. After finding the best topology according to the priority list above, CTPKS satisfies the minimum delay constraint by adding appropriate padding buffers. MG74K/75K/76K Oki Semiconductor 11 ...
Page 14
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 15
... Floorplanning Gate-Level Simulation and Static Timing Analysis Test Vector Conversion Formal Verification Pre-Layout Simulation Automatic Test Pattern Generation Verification (Design Rule Fault Simulation Check/Formal Verification) Figure 5. Oki’s Design Process MG74K/75K/76K [4] Level 1 CAE Front-End Level 2 [3] (Oki TPL ) [2] TDC [4] Level 2.5 Oki Interface ...
Page 16
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 17
... Synthesis (Initial) Chip Level Netlist (1) Floor Plan (1) RC* Synthesis (Detail) Chip Level Netlist (2) DEF RC* SDF Block-level Physical Design RC* SDF RC* - Supports SPEF and DSPF Figure 7. Design Flow MG74K/75K/76K Block level Netlist RC* Delay Calculation SDF Block level STA Block Level Optimization (Optional) Oki Semiconductor 15 ...
Page 18
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 19
... Lead Pitch (mm) 0.80 1. I/O Pads can be used for input, output, bi-directional, power, or ground. = Available # = Planning TQFP LQFP 64 80 100 128 144 176 # 0.50 0.50 0.50 0.40 0.50 0.50 MG74K/75K/76K QFP 208 100 208 # # # # # # # # # # # # # ...
Page 20
... MG74K/75K/76K ––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––– ...
Page 21
... Oki Semiconductor reserves the right to make changes in specifications at anytime and without notice. This information furnished by Oki Semiconductor in this publication is believed to be accurate and reliable. However, no responsibility is assumed by Oki Semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. No license is granted under any patents or patent rights of Oki ...
Page 22
Oki R EGIONAL Silicon Solutions Northwest Area 785 N. Mary Avenue Sunnyvale, CA 94085 Tel: 408/720-8940 Fax:408/720-8965 Northeast Area Shattuck Office Center 138 River Road Andover, MA 01810 Tel: 978/688-8687 Fax:978/688-8896 S O ALES FFICES Southwest Area 1902 Wright Place, ...