CYWUSB6934 Cypress Semiconductor Corporation., CYWUSB6934 Datasheet - Page 13
CYWUSB6934
Manufacturer Part Number
CYWUSB6934
Description
Ls 2.4-ghz Dsss Radio Soc
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
1.CYWUSB6934.pdf
(30 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CYWUSB6934
Manufacturer:
KODENSHI
Quantity:
10 000
Company:
Part Number:
CYWUSB6934-28SEC
Manufacturer:
CY
Quantity:
22 751
Company:
Part Number:
CYWUSB6934-48LFC
Manufacturer:
CY
Quantity:
2 902
Part Number:
CYWUSB6934-48LFC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Company:
Part Number:
CYWUSB6934-48LFXC
Manufacturer:
CY
Quantity:
9 194
Part Number:
CYWUSB6934-48LFXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Part Number:
CYWUSB6934-48LTXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Document 38-16007 Rev. *I
Bit
7:0
Bit
7:0
Bit
7:0
Bit
7:0
Name
Valid
Name
Data
Name
Valid
Name
Data
7
7
7
7
Addr: 0x0A
Addr: 0x0B
Addr: 0x0C
Addr: 0x09
Description
These bits indicate which of the bits in the Receive SERDES Data B register (Reg 0x0B) are valid. A “1” indicates that the
corresponding data bit is valid for Channel B.
If the Valid Data bit is set in the Receive Interrupt Status register (0x08) all eight bits in the Receive SERDES Data B register
(Reg 0x0B) are valid. Therefore, it is not necessary to read the Receive SERDES Valid B register (Reg 0x0C). This register is
read-only.
Description
Received Data for Channel A. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
Description
These bits indicate which of the bits in the Receive SERDES Data A register (Reg 0x09) are valid. A “1” indicates that the
corresponding data bit is valid for Channel A.
If the Valid Data bit is set in the Receive Interrupt Status register (Reg 0x08) all eight bits in the Receive SERDES Data A register
(Reg 0x0A) are valid. Therefore, it is not necessary to read the Receive SERDES Valid A register (Reg 0x0C). This register is
read-only.
Description
Received Data for Channel B. The over-the-air received order is bit 0 followed by bit 1, followed by bit 2, followed by bit 3,
followed by bit 4, followed by bit 5, followed by bit 6, followed by bit 7. This register is read-only.
6
6
6
6
5
5
5
5
Figure 7-11. Receive SERDES Valid B
Figure 7-10. Receive SERDES Data B
Figure 7-9. Receive SERDES Valid A
Figure 7-8. Receive SERDES Data A
REG_RX_VALID_A
REG_RX_VALID_B
REG_RX_DATA_A
REG_RX_DATA_B
4
4
4
4
Data
Valid
Data
Valid
3
3
3
3
2
2
2
2
1
1
1
1
CYWUSB6932
CYWUSB6934
Default: 0x00
Default: 0x00
Default: 0x00
Default: 0x00
Page 13 of 30
0
0
0
0