MSC7116_08 Motorola Semiconductor Products, MSC7116_08 Datasheet

MSC7116_08

Manufacturer Part Number

MSC7116_08

Description

Low-cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Manufacturer

Motorola Semiconductor Products

Datasheet

1.MSC7116_08.pdf (60 pages)

Current page: 1 of 60
Download datasheet (697Kb)

Freescale Semiconductor

Data Sheet

Low-Cost 16-bit DSP with

DDR Controller and 10/100

Mbps Ethernet MAC

• StarCore

• 192 Kbyte M2 memory for critical data and temporary data

• 8 Kbyte boot ROM.

• AHB-Lite crossbar switch that allows parallel data transfers

• Internal PLL generates up to 266 MHz clock for the SC1400 core

• Clock synthesis module provides predivision of PLL input clock;

• Enhanced 16-bit wide host interface (HDI16) provides a glueless

• DDR memory controller that supports byte enables for up to a

• Programmable memory interface with independent read buffers,

• System control unit performs software watchdog timer function;

• Event port collects and counts important signal events including

core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte

instruction cache (ICache), four-entry write buffer, programmable

interrupt controller (PIC), and low-power Wait and Stop

processing modes.

buffering.

between four master ports and six slave ports, where each port

connects to an AHB-Lite bus; fixed or round robin priority

programmable at each slave port; programmable bus parking at

each slave port; low power mode.

and up to 133 MHz for the crossbar switch, DMA channels, M2

memory, and other peripherals.

independent clocking of the internal timers and DDR module;

programmable operation in the SC1400 low power Stop mode;

independent shutdown of different regions of the device.

connection to industry-standard microcomputers,

microprocessors, and DSPs and can also operate with an 8-bit host

data bus, making if fully compatible with the DSP56300 HI08

from the external host side.

32-bit data bus; glueless interface to 133 MHz 14-bit page mode

DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;

and 16-bit or 32-bit external data bus.

programmable predictive read feature for each buffer, and a write

buffer.

includes programmable bus time-out monitors on AHB-Lite slave

buses; includes bus error detection and programmable time-out

monitors on AHB-Lite master buses; and has address

out-of-range detection on each crossbar switch buses.

DMA and interrupt requests and trigger events such as interrupts,

breakpoints, DMA transfers, or wake-up events; units operate

independently, in sequence, or triggered externally; can be used

standalone or with the OCE10.

SC1400 DSP extended core with one SC1400 DSP

• Multi-channel DMA controller with 32 time-multiplexed

• Two independent TDM modules with independent receive and

• Ethernet controller with support for 10/100 Mbps MII/RMII

• UART with full-duplex operation up to 5.0 Mbps.

• Up to 41 general-purpose input/output (GPIO) ports.

• I

• Two quad timer modules, each with sixteen configurable 16-bit

• fieldBIST™ unit detects and provides visibility into unlikely field

• Standard JTAG interface allows easy integration to system

• Optional booting external host via 8-bit or 16-bit access through

unidirectional channels, priority-based time-multiplexing

between channels using 32 internal priority levels, fixed- or

round-robin-priority operation, major-minor loop structure, and

DONE or DRACK protocol from requesting units.

transmit, programmable sharing of frame sync and clock,

programmable word size (8 or 16-bit), hardware-base

A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to

128 channels, with glueless interface to E1/T1 frames and MVIP,

SCAS, and H.110 buses.

designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™,

and 802.3ac™; with internal receive and transmit FIFOs and a

FIFO controller; direct access to internal memories via its own

DMA controller; full and half duplex operation; programmable

maximum frame length; virtual local area network (VLAN) tag

and priority support; retransmission of transmit FIFO following

collision; CRC generation and verification for inbound and

outbound packets; and address recognition including

promiscuous, broadcast, individual address. hash/exact match,

and multicast hash match.

Mbyte.

timers.

failures for systems with high availability to ensure structural

integrity, that the device operates at the rated speed, is free from

reliability defects, and reports diagnostics for partial or complete

device inoperability.

firmware and internal on-chip emulation (OCE10) module.

the HDI16, I

Flash/EEPROM devices; different clocking options during boot

with the PLL on or off using a variety of input frequency ranges.

C interface that allows booting from EEPROM devices up to 1

C, or SPI using in the boot ROM to access serial SPI

MSC7116

Document Number: MSC7116

MAP-BGA–400

17 mm × 17 mm

Rev. 13, 4/2008

Related parts for MSC7116_08

MSC7116_08 Summary of contents

Page 1

Freescale Semiconductor Data Sheet Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC ® • StarCore SC1400 DSP extended core with one SC1400 DSP core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte instruction cache ...

Page 2

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1 ...

Page 3

JTAG Port (32 Channel) JTAG Extended SC1400 Core Trace Buffer (8 KB) Fetch Unit Instruction Cache (16 KB) Extended Core Interface M1 SRAM (192 KB) 128 Note: The arrows show the direction of the transfer. ...

Page 4

Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC7116 package ball grid array layouts and pinout allocation tables. 1.1 MAP-BGA Ball Layout Diagrams Top and bottom views of the MAP-BGA package are shown in Figure 2 and ...

Page 5

BM3 DDIO ...

Page 6

Pin Assignments 1.2 Signal List By Ball Location Table 1 lists the signals sorted by ball number and configuration. Table 1. MSC7116 Signals by Ball Designator Number End of Reset GPI Enabled ...

Page 7

Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled B14 B15 BM2 B16 B17 B18 B19 B20 C10 C11 C12 C13 C14 C15 C16 C17 C18 ...

Page 8

Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E10 E11 E12 E13 ...

Page 9

Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 G10 G11 ...

Page 10

Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 ...

Page 11

Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled J18 J19 J20 HDSP K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 L1 L2 ...

Page 12

Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled L14 L15 L16 L17 L18 L19 L20 M10 M11 M12 M13 M14 M15 M16 M17 ...

Page 13

Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 GPIA15 N20 P10 P11 P12 P13 P14 ...

Page 14

Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 ...

Page 15

Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 ...

Page 16

Pin Assignments Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled V18 GPIA24 V19 V20 GPIA17 W10 BM0 W11 GPIA10 W12 GPIA7 W13 GPIA3 W14 GPIA1 ...

Page 17

Table 1. MSC7116 Signals by Ball Designator (continued) Number End of Reset GPI Enabled Y14 GPIA2 Y15 GPIA29 Y16 Y17 GPIA20 Y18 GPIA21 Y19 Y20 GPIA25 2 Electrical Characteristics This document contains detailed information on power considerations, DC/AC electrical characteristics, ...

Page 18

Electrical Characteristics Table 2 describes the maximum electrical ratings for the MSC7116. Rating Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Input voltage Reference voltage Maximum operating temperature Minimum operating temperature Storage temperature range Notes: 1. ...

Page 19

Thermal Characteristics Table 4 describes thermal characteristics of the MSC7116 for the MAP-BGA package. Table 4. Thermal Characteristics for MAP-BGA Package Characteristic 1, 2 Junction-to-ambient 1, 3 Junction-to-ambient, four-layer board 4 Junction-to-board 5 Junction-to-case 6 Junction-to-package-top Notes: 1. Junction ...

Page 20

Electrical Characteristics Table 5. DC Electrical Characteristics (continued) Characteristic Tri-state (high impedance off state) leakage current DDIO Signal low input current 0 Signal high input current 2 Output ...

Page 21

AC Timings This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC timings are based load, except where noted otherwise, and a 50 Ω transmission line. For ...

Page 22

Electrical Characteristics 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7116 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): ...

Page 23

Multiplication Factor Range The multiplier block output frequency ranges depend on the divided input clock frequency as shown in Table 10. Multiplier Block (Loop) Output Range 266 ≤ [Divided Input Clock × (PLLMLTF + 1)] ≤ 532 MHz Note: ...

Page 24

Electrical Characteristics 2.5.3 Reset Timing The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register ...

Page 25

Reset Configuration The MSC7116 has two mechanisms for writing the reset configuration: • From a host through the host interface (HDI16) 2 • From memory through the I Five signal levels (see Chapter 1 for signal description details) are ...

Page 26

Electrical Characteristics 2.5.4 DDR DRAM Controller Timing This section provides the AC electrical characteristics for the DDR DRAM interface. 2.5.4.1 DDR DRAM Input AC Timing Specifications Table 17 provides the input AC timing specifications for the DDR DRAM interface. No. ...

Page 27

Table 18. DDR DRAM Output AC Timing (continued) No. Parameter 209 Dn/DQMn output setup with respect to DQSn 210 Dn/DQMn output hold with respect to DQSn 4 211 DQSn preamble start 5 212 DQSn epilogue end Notes: 1. All CK/CK ...

Page 28

Electrical Characteristics Figure 7 provides the AC test load for the DDR DRAM bus. Output Table 19. DDR DRAM Measurement Conditions OUT Notes: 1. Data input threshold measurement point. 2. Data output measurement point. 2.5.5 ...

Page 29

TDMxTCK TDMxTD TDMxRCK TDMxTFS (output) TDMxTFS (input) 2.5.6 Ethernet Timing 2.5.6.1 Receive Signal Timing No. 800 Receive clock period: • MII: RXCLK (max frequency = 25 MHz) • RMII: REFCLK (max frequency = 50 MHz) 801 Receive clock pulse width ...

Page 30

Electrical Characteristics 2.5.6.2 Transmit Signal Timing No. 800 Transmit clock period: • MII: TXCLK • RMII: REFCLK 801 Transmit clock pulse width high—as a percent of clock period • MII: RXCLK • RMII: REFCLK 802 Transmit clock pulse width low—as ...

Page 31

Management Interface Timing Table 24. Ethernet Controller Management Interface Timing No. 808 MDC period 809 MDC pulse width high 810 MDC pulse width low 811 MDS falling edge to MDIO output invalid (minimum propagation delay) 812 MDS falling edge ...

Page 32

Electrical Characteristics 2.5.7 HDI16 Signals No. Characteristics 40 Host Interface Clock period 44a Read data strobe minimum assertion width HACK read minimum assertion width 44b Read data strobe minimum deassertion width HACK read minimum deassertion width 44c Read data strobe ...

Page 33

Figure 14 and Figure 15 show HDI16 read signal timing. Figure 16 and Figure 17 show HDI16 write signal timing. HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 14. Read Timing Diagram, Single Data Strobe HA[0–2] ...

Page 34

HA[0–2] HCS[1–2] HRW HDS HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 16. Write Timing Diagram, Single Data Strobe HA[0–2] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 17. Write Timing Diagram, Double Data Strobe ...

Page 35

Figure 18. Host DMA Read Timing Diagram, HPCR[OAD HD[0–15] Figure 19. Host DMA Write Timing Diagram, HPCR[OAD Freescale Semiconductor HREQ (Output) 64 44a RX[0–3] HACK Read 50 49 Data HD[0–15] Valid (Output) HREQ (Output ...

Page 36

I C Timing No. Characteristic 450 SCL clock frequency 451 Hold time START condition 452 SCL low period 453 SCL high period 454 Repeated START set-up time (not shown in figure) 455 Data hold time 456 Data set-up ...

Page 37

UART Timing No. Characteristics — Internal bus clock (APBCLK) — Internal bus clock period (1/APBCLK) 400 URXD and UTXD inputs high/low duration 401 URXD and UTXD inputs rise/fall time 402 UTXD output rise/fall time UTXD, URXD inputs UTXD Output ...

Page 38

Event Timing Number Characteristics 67 EVNT as input 68 EVNT as output Notes: 1. Refer to Table 27 for a definition of the APBCLK period. 2. Direction of the EVNT signal is configured through the GPIO and Event port ...

Page 39

JTAG Signals No. Characteristics 700 TCK frequency of operation (1/(T Note 1/CLOCK which is the period of the core clock. The TCK C frequency must less than 1/3 of the core frequency with an absolute maximum limit ...

Page 40

TCK V (Input) IL Data Inputs Data Outputs Data Outputs Figure 27. Boundary Scan (JTAG) Timing Diagram TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) Figure 28. Test Access Port Timing Diagram TRST (Input) 712 40 704 ...

Page 41

Hardware Design Considerations This section described various areas to consider when incorporating the MSC7116 device into a system design. 3.1 Thermal Design Considerations An estimation of the chip-junction temperature where T = ambient temperature near the package (°C) A ...

Page 42

Hardware Design Considerations 3.2 Power Supply Design Considerations This section outlines the MSC7116 power considerations: power supply, power sequencing, power planes, decoupling, power supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power ...

Page 43

Case 1 The power-up sequence is as follows: 1. Turn on the V (3.3 V) supply first. DDIO 2. Turn on the V (1.2 V) supply second. DDC 3. Turn on the V (2.5 V) supply third. DDM 4. ...

Page 44

Hardware Design Considerations 3.2.2.2 Case 2 The power-up sequence is as follows: 1. Turn on the V (3.3 V) supply first. DDIO 2. Turn on the V (1.2 V) and V DDC 3. Turn on the V (1.25 V) supply ...

Page 45

Case 3 The power-up sequence is as follows: 1. Turn on the V (3.3 V) supply first. DDIO 2. Turn on the V (1.2 V) supply second. DDC 3. Turn on the V (2.5 V) and V DDM Note: ...

Page 46

Hardware Design Considerations 3.2.2.4 Case 4 The power-up sequence is as follows: 1. Turn on the V (3.3 V) supply first. DDIO 2. Turn on the V (1.2 V), V DDC Note: Make sure that the time interval between the ...

Page 47

Case 5 (not recommended for new designs) The power-up sequence is as follows: 1. Turn on the V (3.3 V) supply first. DDIO 2. Turn on the V (2.5 V) supply second. DDM 3. Turn on the V (1.2 ...

Page 48

Hardware Design Considerations 3.2.3 Power Planes Each power supply pin ( and DDC DDM, should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device. The MSC7116 ...

Page 49

Power Supply Design One of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator. For the system I/O voltage supply, a simple fixed 3.3 V supply can be used. However, ...

Page 50

Hardware Design Considerations 3.3.2 Peripheral Power Peripherals include the DDR memory controller, Ethernet controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, 2 and the I C module. Basic power consumption by each module is assumed to be the same and ...

Page 51

Example Total Power Consumption Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is estimated as the following: = 287 + (4 × 3.83) + 326.3 + (10 ...

Page 52

Hardware Design Considerations Boot Input Clock BM[3–0] Port Frequency HDI Boot Modes < F 0000 HDI16 max 0101 HDI16 22.2-25 MHz 0010 HDI16 25-33.3 MHz 0111 HDI16 33-66 MHz 0100 HDI16 44.3-50 MHz SPI Boot Modes - Using HA3, HCS2, ...

Page 53

When booting from a power-on reset, the HDI16 is additionally configurable as follows: • 16-bit mode as specified by the • Data strobe as specified by the These pins are sampled only on the deassertion of power-on reset. ...

Page 54

Hardware Design Considerations 3.5 DDR Memory System Guidelines MSC7116 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are ...

Page 55

Driver V DDQ 3.5.1 V and V Design Constraints REF TT V and V are isolated power supplies at the same voltage, with V TT REF the voltage supply design needs and goals: • Minimize the noise on both rails. ...

Page 56

Hardware Design Considerations 3.5.3 General Routing The general routing considerations for the DDR are as follows: • All DDR signals must be routed next to a solid reference: — For data, next to solid ground planes. — For address/command, power ...

Page 57

Connectivity Guidelines This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7116 device. Following are guidelines for signal groups and configuration settings: • Clock and reset signals. — is used to configure ...

Page 58

Package Information 5 Package Information Figure 38. MSC7116 Mechanical Information, 400-pin MAP-BGA Package 6 Product Documentation • MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application ...

Page 59

Revision History Table 36 provides a revision history for this data sheet. Revision Date 0 Apr 2004 • Initial public release. 1 May 2004 • Added ordering information and new package options. 2 Aug. 2004 • Updated clock parameter ...

Page 60

How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter ...

Related keywords

MSC7116_08 datasheet
MSC7116_08 data sheet
MSC7116_08 pdf datasheet
MSC7116_08 component
MSC7116_08 part
MSC7116_08 distributor
MSC7116_08 RoHS
MSC7116_08 datasheet download