MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet
MSC7115
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MSC7115 Summary of contents
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... DMA transfers, or wake-up events; units operate independently, in sequence, or triggered externally; can be used standalone or with the OCE10. © Freescale Semiconductor, Inc., 2004, 2008. All rights reserved. Document Number: MSC7115 MSC7115 MAP-BGA–400 17 mm × • Multi-channel DMA controller with 32 time-multiplexed ...
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... Package Information .54 6 Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 7 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 List of Figures Figure 1. MSC7115 Block Diagram Figure 2. MSC7115 Molded Array Process-Ball Grid Array (MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. MSC7115 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5 Figure 4. Timing Diagram for a Reset Configuration Write . . . . 24 Figure 5 ...
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... Cache (16 KB) Extended Core Interface M1 SRAM (256 KB) 128 Note: The arrows show the direction of the transfer. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor DMA AMDMA ASM2 128 64 to IPBus 64 DSP ASEMI Core 64 IPBus ASTH ...
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... Pin Assignments 1 Pin Assignments This section includes diagrams of the MSC7115 package ball grid array layouts and pinout allocation tables. 1.1 MAP-BGA Ball Layout Diagrams Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers. ...
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... H8BIT GPIA26 GPIA23 GPIA19 T2TFS T2RFS T1TFS Y GPIA25 GND GPIA21 GPIA20 T2TCK T2RCK T1TCK T1RCK Figure 3. MSC7115 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Bottom View ...
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... A19 A20 B10 B11 B12 B13 B14 B15 (1L44X) MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND DQM1 DQS2 CK CK GPIC7 GPOC7 GPIC4 ...
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... C15 C16 C17 C18 C19 C20 D10 D11 D12 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GPID7 GPOD7 D24 D30 D25 ...
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... E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F10 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDIO V DDIO V DDIO V DDIO V DDC NC NC ...
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... G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDM GND GND GND V DDIO V DDC V ...
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... J13 J14 J15 J16 J17 J18 (1L44X) J18 (1M88B) J19 J20 HDSP MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND GND GND GND GND V DDIO ...
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... L11 L12 L13 L14 L15 L16 L17 L18 (1L44X) L18 (1M88B) L19 L20 M1 M2 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GND GND GND GND GND GND ...
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... N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 GPIA15 N20 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D5 V DDM V DDM GND GND GND GND ...
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... R10 R11 R12 R13 R14 R15 R16 R17 R18 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled D7 D17 D16 V DDM V DDM V DDM GND GND ...
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... T18 T19 T20 U10 U11 U12 U13 U14 U15 U16 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled reserved TEST0 V DDM D20 D22 V DDM V DDM V ...
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... GPIA17 W10 BM0 W11 GPIA10 W12 GPIA7 W13 GPIA3 W14 GPIA1 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled V DDC NC TCK TRST V DDM NC A13 A11 ...
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... Y13 GPIA5 Y14 GPIA2 Y15 GPIA29 Y16 Y17 GPIA20 Y18 GPIA21 Y19 Y20 GPIA25 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Signal Names Software Controlled Interrupt GPO Enabled (Default) Enabled GPID4 GPOD4 IRQ18 GPOA27 IRQ19 GPOA19 IRQ23 ...
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... MSC711x Reference Manual. Note: The MSC7115 electrical specifications are preliminary and many are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after thorough characterization and device qualifications have been completed. ...
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... Core supply voltage Memory supply voltage PLL supply voltage I/O supply voltage Reference voltage Operating temperature range 2.3 Thermal Characteristics Table 4 describes thermal characteristics of the MSC7115 for the MAP-BGA package. Table 4. Thermal Characteristics for MAP-BGA Package Characteristic 1, 2 Junction-to-ambient 1, 3 Junction-to-ambient, four-layer board 4 ...
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... V REF exceed ±2% of the DC value not applied directly to the MSC7115 device the level measured at the far end signal termination. It should be equal This rail should track variations in the DC level of V REF Output leakage for the memory interface is measured with all outputs disabled ≤ ...
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... CLKO frequency jitter (peak-to-peak) 2.5.2 Configuring Clock Frequencies This section describes important requirements for configuring clock frequencies in the MSC7115 device when using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL): • PLLDVF field. Specifies the PLL division factor. The output of the divider block is the input to the multiplier block. ...
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... Note: This table results from the allowed range for F This bit along with the CKSEL determines the frequency range of the core clock. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor CLKIN frequency range, as shown in Table 10. 10.5 to 19.5 MHz ...
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... Reset Timing The MSC7115 device has several inputs to the reset logic. All MSC7115 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 15 describes the reset sources. ...
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... No. 1 Required external PORESET duration minimum 2 Delay from PORESET deassertion to HRESET deassertion Note: Timings are not tested, but are guaranteed by design. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Power-On Reset (PORESET) External only Yes Yes Yes ...
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... Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is done internally. DQSn Dn Note: DQS centering is done internally. Figure 5. DDR DRAM Input Timing Diagram MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Configuration Pins are sampled 2 Table 18. DDR DRAM Input AC Timing ...
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... JEDEC does not require this device limitation, but simply for the chip to guarantee fast enough write to read turn-around times. This is already guaranteed by the memory controller operation. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Table 19 ...
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... TDMxRCK/TDMxTCK Low Pulse Width 303 TDM all input Setup time 304 TDMxRD Hold time 305 TDMxTFS/TDMxRFS input Hold time 306 TDMxTCK High to TDMxTD output active MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev 200 205 207 NOOP 211 208 209 ...
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... Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge. TDMxRCK TDMxRD TDMxRFS TDMxRFS (output) TDMxTCK TDMxTD TDMxRCK TDMxTFS (output) TDMxTFS (input) MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Table 21. TDM Timing Expression 300 301 304 303 305 303 310 Figure 8 ...
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... Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) deassertion to HREQ assertion. 64 Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) assertion to HREQ deassertion MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 22. Host Interface (HDI16) Timing Mask Set 1L44X ...
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... HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HRRQ (double host request) Figure 10. Read Timing Diagram, Single Data Strobe MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Mask Set 1L44X 3 Expression = 10 ns core clock period. At 266 MHz, T ...
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... Figure 11. Read Timing Diagram, Double Data Strobe HA[0–3] HCS[1–2] HRW HDS HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 12. Write Timing Diagram, Single Data Strobe MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev 44a ...
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... HA[0–3] HCS[1–2] HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 13. Write Timing Diagram, Double Data Strobe Figure 14. Host DMA Read Timing Diagram, HPCR[OAD MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor HWR ...
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... HD[0–15] Figure 15. Host DMA Write Timing Diagram, HPCR[OAD MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev HREQ (Output TX[0–3] Write HACK 47 Data Valid (Input Freescale Semiconductor ...
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... SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance on SDA and SCL is 400 pF. Start Condition 1 SCL 451 SDA 458 Start Condition SCL SDA MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor 2 Table 23 Timing Min 0 (Clock period/2) – 0.3 (Clock period/2) – 0.3 (Clock period/2) – 0.1 2 × 1/F ...
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... Configure the direction of the EE pin in the EE_CTRL register (see the SC1400 Core Reference Manual for details. 3. Refer to Table 15 for details on EE pin functionality. Figure 19 shows the signal behavior of the EE0 in EE0 out MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 24. UART Timing Expression F /2 ...
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... Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is acknowledged. Figure 21 shows the signal behavior of the GPI GPO MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Table 26. EVNT Signal Timing Type Asynchronous Synchronous to core clock pin ...
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... All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface. TCK (Input) Figure 22. Test Clock Input Timing Diagram MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Table 28. JTAG Timing × 3); maximum 22 MHz ...
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... TMS (Input) TDO (Output) TDO (Output) Figure 24. Test Access Port Timing Diagram TRST (Input) 712 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor 704 Input Data Valid 706 Output Data Valid 707 708 Input Data Valid 710 ...
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... I/O The power dissipation values for the MSC7115 are listed in Table 4. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes ...
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... Core Memory Reference I/O You should supply the MSC7115 core voltage via a variable switching supply or regulator to allow for compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across V and GND and the I/O section is supplied with 3.3 V (± 10%) across V the DDR memory controller block. The memory voltage is supplied with 2.5 V across V and must be between 0.49 × ...
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... Make sure that the time interval between the ramp-up or ramp-down for V power-up and power-down. • Refer to Figure 26 for relative timing for power sequencing case 1. Ramp-up <10 ms <10 ms MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev and V DDIO <10 ms Time Figure 26. Voltage Sequencing Case 1 is less than 10 ms ...
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... Make sure that the time interval between the ramp-up or ramp-down for V power-up and power-down. • Refer to Figure 27 for relative timing for Case 2. Ramp-up <10 ms MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor (2.5 V) supplies simultaneously (second). DDM and V DDIO ...
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... Make sure that the time interval between the ramp-up or ramp-down time for V power-up and power-down. • Refer to Figure 28 for relative timing for Case 3. Ramp-up <10 ms <10 ms MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev (1.25 V) supplies simultaneously (third). REF and V DDIO (1.25 V) supplies simultaneously (first). ...
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... Make sure that the time interval between the ramp-up or ramp-down time for V power-up and power-down. • Refer to Figure 29 for relative timing for Case 4. Ramp-up <10 ms MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor (2.5 V), and V (1.25 V) supplies simultaneously (second). DDM REF ...
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... If a design uses case 5, it must accommodate DDM the potential current spikes. Verify risks related to current spikes using actual information for the specific application. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev and V ...
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... The second decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7115 voltage pins. Additionally, the maximum drop between the power supply and the DSP device should ...
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... V, and the core frequency is 200 MHz or 266 MHz. This yields: P CORE P CORE This equation allows for adjustments to voltage and frequency if necessary. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev Symbol Nominal Voltage V DDC ...
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... Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7115 device, the 2.5 V power source provides the power for the termination, which is a static value per signal driven high. ...
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... Either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7115 output current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design). ...
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... ROM. After initialization, the DSP core can enable the PLL and start the device operating at a higher speed. The MSC7115 can boot from an external host through the HDI16 or download a user program through the I ...
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... For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual. 3.5 DDR Memory System Guidelines MSC7115 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown in Figure 32 ...
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... TT termination rail. • See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel (http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf). MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor ...
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... If stack-up allows, keep DDR data groups away from the address and control nets. — Route address and control on separate critical layers. — If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages. MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev DQS ...
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... Connectivity Guidelines This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7115 device. Following are guidelines for signal groups and configuration settings: • Clock and reset signals. — is used to configure the MSC7115 device and is sampled on the deassertion of ...
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... MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the internal subsystems including configuration and programming information. • Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7115 device. • SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock registers, program control, and instruction set ...
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... These cases replace the previously recommended power-up/power-down sequence recommendations. The section has been clarified by adding subsection headings. • Change the PLL filter resistor from 20 Ω Ω in Section 3.2.5. 11 Apr 2008 MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11 Freescale Semiconductor Table 33. Document Revision History Description 2 C timing specifications ...
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... Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MSC7115 Rev. 11 4/2008 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document ...