MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 47

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

3.3.2
Peripherals include the DDR memory controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the I
Basic power consumption by each module is assumed to be the same and is computed by using the following equation which
assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100 MH or 133 MHz. This yields:
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7115
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
As an example, assume the following:
In this example, the DDR memory power consumption is:
Freescale Semiconductor
pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity)
P
P
DDRIO
DDRIO
= ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
= ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)
Peripheral Power
External Memory Power
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
P
P
P
PERIPHERAL
PERIPHERAL
P
DYNAMIC
DYNAMIC
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
P
STATIC
= (pin activity value) × 20 pF × (0.4 V)
= (pin activity value) × 20 pF × (0.4 V)
= 20 pF × (1.2 V)
= 20 pF × (1.2 V)
= (unused pins × % driven high) × 16 mA × 2.5 V
P
DDRIO
2
2
= P
× 100 MHz × 10
× 133 MHz × 10
STATIC
+ P
DYNAMIC
–3
–3
2
2
= 2.88 mW per peripheral
= 3.83 mW per peripheral
× 266 MHz × 10
× 200 MHz × 10
2
2
× 200 × 10
× 266 × 10
–3
–3
Hardware Design Considerations
mW
mW
–3
–3
) = 324.2 mW
) = 326.3 mW
2
C module.
Eqn. 10
Eqn. 12
Eqn. 13
Eqn. 14
Eqn. 15
Eqn. 11
Eqn. 7
Eqn. 8
Eqn. 9
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