MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 48

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

Hardware Design Considerations
3.3.4
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 25 MHz or
33 MHz, which yields:
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.
Note:
3.3.5
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
3.3.6
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
3.4
This section describes the recommendations for configuring the MSC7115 at reset and boot.
3.4.1
HRESET
an open-drain output such as
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7115 output
current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design).
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The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as
7 pF.
is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
Reset and Boot
External I/O Power
Leakage Power
Example Total Power Consumption
Reset Circuit
P
P
TOTAL
TOTAL
(200 MHz core) = 216 + (4 × 2.88) + 324,2 + (10 × 5.44) + 64 = 670.12 mW
(266 MHz core) = 287 + (4 × 3.83) + 326.3 + (10 × 7.19) + 64 = 764.52 mW
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
P
P
IO
IO
HRESET
= 20 pF × (3.3 V)
= 20 pF × (3.3 V)
, take care when driving many buffers that implement input bus-hold circuitry. The
2
2
× 25 MHz × 10
× 33 MHz × 10
–3
–3
= 5.44 mW per I/O line
= 7.19 mW per I/O line
Freescale Semiconductor
Eqn. 16
Eqn. 17
Eqn. 18
Eqn. 19