MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 2

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

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List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1
1.2
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1
2.2
2.3
2.4
2.5
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .38
3.1
3.2
3.3
3.4
3.5
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4
Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Recommended Operating Conditions. . . . . . . . . . . . . .18
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Thermal Design Considerations . . . . . . . . . . . . . . . . . .38
Power Supply Design Considerations. . . . . . . . . . . . . .39
Estimated Power Usage Calculations. . . . . . . . . . . . . .46
Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
DDR Memory System Guidelines . . . . . . . . . . . . . . . . .50
MSC7115 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
MSC7115 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
MSC7115 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram for a Reset Configuration Write . . . . 24
DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 24
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Table of Contents
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10. Read Timing Diagram, Single Data Strobe . . . . . . . . 29
Figure 11. Read Timing Diagram, Double Data Strobe . . . . . . . . 30
Figure 12. Write Timing Diagram, Single Data Strobe. . . . . . . . . 30
Figure 13. Write Timing Diagram, Double Data Strobe . . . . . . . . 31
Figure 14. Host DMA Read Timing Diagram, HPCR[OAD] = 0 . . 31
Figure 15. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 32
Figure 16. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 36
Figure 23. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 37
Figure 24. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 37
Figure 25. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . . 40
Figure 27. Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . . 41
Figure 28. Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . . 42
Figure 29. Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . . 43
Figure 30. Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . . 44
Figure 31. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 45
Figure 32. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 50
Figure 33. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 26
DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . . 26
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 27
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 27
Freescale Semiconductor