MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 28

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

Specifications
2.5.6
28
No.
44a Read data strobe minimum assertion width
44b Read data strobe minimum deassertion width
44c Read data strobe minimum deassertion width
40 Host Interface Clock period
45 Write data strobe minimum assertion width
46 Write data strobe minimum deassertion width
47 Host data input minimum setup time before write data strobe
48 Host data input minimum hold time after write data strobe
49 Read data strobe minimum assertion to output data active from high
50 Read data strobe maximum assertion to output data valid
51 Read data strobe maximum deassertion to output data high
52 Output data minimum hold time after read data strobe deassertion
53 HCS[1–2] minimum assertion to read data strobe assertion
54 HCS[1–2] minimum assertion to write data strobe assertion
55 HCS[1–2] maximum assertion to output data valid
56 HCS[1–2] minimum hold time after data strobe deassertion
57 HA[0–3], HRW minimum setup time before data strobe assertion
58 HA[0–3], HRW minimum hold time after data strobe deassertion
61 Maximum delay from read data strobe deassertion to host request
62 Maximum delay from write data strobe deassertion to host request
63 Minimum delay from DMA HACK (OAD=0) or Read/Write data
64 Maximum delay from DMA HACK (OAD=0) or Read/Write data
HACK read minimum assertion width
HACK read minimum deassertion width
Register” reads
reads
HACK minimum deassertion width after “Last Data Register” reads
HACK write minimum assertion width
HACK write minimum deassertion width after ICR, CVR and Data
Register writes
deassertion
Host data input minimum setup time before HACK write deassertion
deassertion
Host data input minimum hold time after HACK write deassertion
impedance
HACK read minimum assertion to output data active from high
impedance
HACK read maximum assertion to output data valid
impedance
HACK read maximum deassertion to output data high impedance
Output data minimum hold time after HACK read deassertion
deassertion for “Last Data Register” read
deassertion for “Last Data Register” write
strobe(OAD=1) deassertion to HREQ assertion.
strobe(OAD=1) assertion to HREQ deassertion
7
HDI16 Signals
4
4
8
8
5
5,6
, or between two consecutive CVR, ICR, or ISR
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Characteristics
Table 22. Host Interface (HDI16) Timing
4, 5, 10
5,8,10
4
8
3
8
4
4
after “Last Data
4
4
9
8
9
9
5,6
4
(2.0 × T
(2.0 × T
(3.0 × T
(3.0 × T
(2.0 × T
(5.0 × T
Expression
3.0 × T
1.5 × T
2.5 × T
1.5 × T
2.5 × T
Mask Set 1L44X
T
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
HCLK
—
—
—
—
—
—
—
—
—
—
HCLK
HCLK
HCLK
HCLK
HCLK
) + 8.0 Note 11 (2.0 × T
) + 8.0 Note 11 (2.0 × T
) + 8.0 Note 11 (3.0 × T
) + 8.0 Note 11 (3.0 × T
) + 1.0 Note 11 (2.0 × T
) + 8.0 Note 11 (5.0 × T
1, 2
Note 11 2.0 × T
Note 11
Note 11
Note 11
Note 11
Value
Note 1
3.0
4.0
1.0
8.0
1.0
0.0
0.0
0.0
5.0
5.0
Expression
1.5 × T
2.5 × T
1.5 × T
2.5 × T
Mask Set 1M88B
T
Freescale Semiconductor
CORE
CORE
CORE
CORE
CORE
CORE
CORE
CORE
—
—
—
—
—
—
—
—
—
—
CORE
CORE
CORE
CORE
) + 8.0 Note 11
) + 6.0 Note 11
) + 6.0 Note 11
) + 6.0 Note 11
) + 1.0 Note 11
) + 6.0 Note 11
+ 9.0 Note 11
Note 11
Note 11
Note 11
Note 11
Value
Note 1
2.5
2.5
1.0
9.0
1.0
0.5
0.0
0.5
5.0
5.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns