MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 20

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

Specifications
2.5
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the
following equations to compute the delay:
2.5.1
The following tables describe clock signal characteristics. Table 7 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (
for the allowable ranges when using the PLL).
2.5.2
This section describes important requirements for configuring clock frequencies in the MSC7115 device when using the PLL
block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the
allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines
to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x
Reference Manual for details on the clock programming model.
20
Core clock frequency (CLOCK)
External output clock frequency (CLKO)
Memory clock frequency (CK, CK)
TDM clock frequency (TxRCK, TxTCK)
CLKIN frequency
CLOCK frequency
CK, CK frequency
TDMxRCK, TDMxTCK frequency
CLKO frequency
AHB/IPBus/APB clock frequency
Note:
CLKIN frequency
CLKIN slope
CLKIN frequency jitter (peak-to-peak)
CLKO frequency jitter (peak-to-peak)
•
•
•
•
•
•
Standard interface: 2.45 + (0.054 × C
DDR interface: 1.6 + (0.002 × C
PLLDVF field. Specifies the PLL division factor. The output of the divider block is the input to the multiplier block.
PLLMLTF field. Specifies the PLL multiplication factor. The output from the multiplier block is the
RNG field. Selects the available PLL frequency range.
CKSEL field. Selects the source for the core clock.
The rise and fall time of external clocks should be 5 ns maximum
AC Timings
Clock and Timing Signals
Configuring Clock Frequencies
Characteristic
Characteristic
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Characteristic
CLKO
load
Table 8. Clock Frequencies in MHz
Table 9. System Clock Parameters
Table 7. Maximum Frequencies
) ns
load
) clocks. You must ensure that maximum frequency values are not exceeded (see
) ns
Symbol
F
F
F
F
TDMCK
F
CLKIN
CORE
F
CKO
BCK
CK
Mask Set 1L44X
Min
10
—
—
—
—
—
200
100
50
50
Min
10
—
—
—
Mask Set 1L44X
Maximum in MHz
100
200
100
100
50
50
Max
1000
100
150
5
Freescale Semiconductor
Max
Mask Set 1M88B
Mask Set 1M88B
266
133
67
67
VCO
100
266
133
133
50
67
.
Unit
MHz
ns
ps
ps