MSC7115 Motorola Semiconductor Products, MSC7115 Datasheet - Page 34

• Manufacturer Part Number: MSC7115
• Manufacturer: Motorola Semiconductor Products

2.5.8
2.5.9
Figure 19 shows the signal behavior of the
34
Notes:
No.
400
401
402
—
—
Number
65
66
Internal bus clock (APBCLK)
Internal bus clock period (1/APBCLK)
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
1.
2.
3.
UART Timing
EE Timing
The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
Configure the direction of the EE pin in the EE_CTRL register (see the SC1400 Core Reference Manual for details.
Refer to Table 15 for details on EE pin functionality.
UTXD, URXD
inputs
UTXD output
EE0 input to the core
EE0 output from the core
MSC7115 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Characteristics
Characteristics
EE0 out
EE0 in
EE
Figure 18. UART Output Timing
Figure 17. UART Input Timing
pin.
401
402
Figure 19. EE Pin Timing
Table 24. UART Timing
Table 25. EE0 Timing
400
Synchronous to core clock
Expression
16 × T
Asynchronous
F
T
APBCLK
CORE
Type
APBCLK
/2
402
66
65
401
160.0
Min
10.0
—
—
—
Mask Set
1L44X
400
Max
100
—
—
5
5
4 core clock periods
1 core clock period
Freescale Semiconductor
120.3
Min
7.52
—
—
—
Mask Set
1M88B
Min
Max
133
—
—
5
5
Unit
MHz
ns
ns
ns
ns