CS2411 Amphion, CS2411 Datasheet - Page 2

• Manufacturer Part Number: CS2411
• Description: User-programmable Fft/ifft 1024-point Block Based
• Manufacturer: Amphion

FFT (Fast Fourier Transform) and IFFT (Inverse Fast Fourier
Transform) are algorithms computing 2
Fourier transform and inverse discrete Fourier transform, as
defined below.
Where N=2
The
proportional to Nlog
FFT/IFFT is performed. The higher the radix, the less number
of multiplication is required, however the more simultaneous
multiple data access is required which causes the circuits to be
more complicated. The radix-4 algorithm offers a balance
between the computational and circuit complexity and is often
used in construction of higher radix FFT computation units
when designing high performance FFT/IFFT hardware.
2
CLK
NotRST
CLR
IFFT
SDC
XRe
XIm
XBS
YEnab
STE*
XBIP
Busy
IFFT:
FFT:
CS2411
Name
computational
Y k ( )
Y k ( )
FAST FOURIER TRANSFORM
P
=
I/O Width
=
and
O
O
I
I
I
I
I
I
I
I
I
I
--- -
N
1
N 1
n
∑
N 1
n
=
–
∑
=
e
0
–
–
X n ( )
0
j2π
X n ( )
13
13
R
1
1
1
1
3
1
1
1
1
1
N, where R is the radix base on which
⁄
complexity
W
N
1024 Point FFT/IFFT
W
N
.
–
N
nk
nk
Clock signal, rising edge active
Asynchronous global reset signal, active LOW
Clear (synchronous reset) and programming signal, active HIGH
Programming signal specifying the transform type, loaded when CLR is active
Programming signal specifying the number of bits for the additional scaling down operation, loaded
when CLR is active
Real component of input data X, in two’s complement format
Imaginary component of input data X, in two’s complement format
Input data X block start signal, active HIGH, associated with the first input data of the 1024-point
block. The remaining data of the 1024-point data block is loaded into the core in the following clock
cycles in the natural order.
Output data Y enable control, active HIGH
Scan Test Enable Signal – ASIC version only
During scan testing the memory block needs to be bypassed to allow the scan test to be performed.
During test STE is set HIGH and the memory is bypassed. During normal operation STE is set LOW.
Output signal indicating loading X is in Progress. XBIP goes to HIGH the next clock cycle when XBS
is active and returns to LOW when the last data of the 1024-point block is loaded into the core. XBS is
ignored when it is HIGH.
Output signal indicating the transform in progress (busy). It goes to HIGH the next clock cycle when
the last data of the 1024-point block is loaded into the core and returns to LOW when the core is ready
to accept the next input data block. XBS is ignored when it is HIGH.
Table 1: CS2411 - 1024 Point FFT / IFFT Interface Signal Definitions
, k=0, 1, 3, ...N-1
, k=0, 1, 3, ...N-+1
of
FFT
p
-point discrete
and
IFFT
[1]
[2]
is
Table 1 describes input and output ports (shown graphically
in Figure 2) of the CS2411 1024-point FFT/IFFT core. Unless
otherwise stated, all signals are active high and bit(0) is the
least significant bit.
Figure 2: CS2411 Symbol
NotRST
YEnab
Description
STE*
IFFT
SDC
CLR
XBS
CLK
XRe
Xlm
AND PIN DESCRIPTION
13
13
3
CS2411 SYMBOL
FFT/IFFT
CS2411
1024-pt
13
13
YRe
Ylm
YOV
YAV
XBIP
Busy
Done
YBS