CMX602BD4 MX-COM, Inc., CMX602BD4 Datasheet - Page 4

• Manufacturer Part Number: CMX602BD4
• Description: Calling line identifier plus call waiting
• Manufacturer: MX-COM, Inc.

Calling Line Identifier plus Call Waiting (Type II)
2. Signal List
Notes: input (S) = Schmitt trigger input
4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA
Pin No.
2000 MX-COM, Inc
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
XTAL
RD
RT
AMPOUT
IN -
IN +
V
V
MODE
ZP
DET
RXCLK
RXD
V
IRQ
XTAL
SS
BIAS
DD
Signal
output
input /
output
output
power
output
output
output
output
power
Type
input
input
input
input
input
input
input
www.mxcom.com Tel: [phone] 744 5050 Fax: [phone]
(S)
(S)
(S)
Output of the on-chip Xtal oscillator inverter
Input to the on-chip Xtal oscillator inverter
Input to the Ring or Line Polarity Reversal Detector
Open-drain output and Schmitt trigger input forming part of the Ring or Line
Polarity Reversal detector. An external resistor to V
V
Output of the on-chip Input Signal Amplifier
Inverting input to the on-chip Input Signal Amplifier
Non-inverting input to the on-chip Input Signal Amplifier
Negative supply
Internally generated bias voltage, held at V
'Zero-Power' mode. Should be bypassed to V
close to the device pins.
Input used to select the Tone Alert or FSK Level Detection operating mode.
See Section 4.1
High level on this input selects 'Zero-Power' mode, a low level input enables
the V
the FSK or the Tone alert circuits depending on the MODE input
Open-drain output (active low) that may be used as an Interrupt Request /
Wake-up input to the associated µC. Indicates CAS Dual Tone event of
correct duration when device is in Tone Alert Detect Mode. An external pull-
up resistor should be connected between this output and V
Logic level output driven by the Ring or Line Polarity Reversal Detector, the
Tone Alert Detector or the FSK Level detect circuits, depending on the
operating mode. When device is in Tone Alert Mode, it may be used as a
near end voice mute control signal. See Section 4.1
Logic level input, which may be used to clock, received data bits out of the
FSK Data Retiming block. When held high disables FSK Data Retiming
block.
Logic level output carrying either the raw output of the FSK Demodulator or
re-timed 8-bit characters depending on the state of the RXCLK input. See
Section 4.6
Positive supply. Levels and thresholds within the device are proportional to
this voltage. Should be bypassed to V
device pins.
SS
should be connected to RT to filter and extend the RD input signal
BIAS
supply, the Input signal amplifier, the Bandpass Filter , and either
Table 1 : Signal List
4
All trademarks and service marks are held by their respective companies.
Description
SS
by a capacitor mounted close to the
DD
CMX602B PRELIMINARY INFORMATION
/2 when the device is not in
SS
by a capacitor mounted
DD
and a capacitor to
DD
Doc. # 20480204.002
.