CMX602BD4 MX-COM, Inc., CMX602BD4 Datasheet - Page 8

• Manufacturer Part Number: CMX602BD4
• Description: Calling line identifier plus call waiting
• Manufacturer: MX-COM, Inc.

Calling Line Identifier plus Call Waiting (Type II)
8
CMX602B PRELIMINARY INFORMATION
4.4 Level Detector
The Level Detector block operates by measuring the level of the signal at the output of the Bandpass Filter. It
then compares it against a threshold, which depends on whether FSK Receive or Tone Alert Detect mode has
been selected.
In Tone Alert Detect mode the output of the Level Detector block provides an input to the Tone Alert Signal
Detector.
In FSK Receive mode the CMX602B DET output will be set high when the level has exceeded the threshold
for a sufficient duration. Amplitude and time hysteresis are used to reduce chattering of the DET output in
marginal conditions.
Note: In FSK Receive mode, this circuit may also respond to non-FSK signals such as speech.
t
DFOFF
Line Signal
FSK signal
t
DFON
DET
MODE, ZP
FSK Receiver mode
See Section 6.1 for definitions of t
and t
DFON
DFOFF
Figure 6: FSK Level Detector Operation
4.5 FSK Demodulator
The FSK Demodulator block converts the 1200 baud FSK input signal to a digital data stream which is output
via the RXD pin as long as the Data Retiming function is not enabled (Holding RXCLK continuously high).
The RXD output does not depend on the state of the FSK Level Detector output.
Note: In the absence of a valid FSK signal, the demodulator may falsely interpret speech or other extraneous
signals as data.
4.6 FSK Data Retiming
The Data Retiming block extracts the 8 data bits of each character from the received asynchronous data
stream and presents them to the C under the control of strobe pulses applied to the RXCLK input. The
timing of these pulses is not critical, and they may easily be generated by a simple software loop. This facility
removes the need for a UART in the C without incurring an excessive software overhead.
The block operates on a character by character basis by first looking for the mark to space transition which
signals the beginning of the start bit. Using this transition as a timing reference, the block samples the output
of the FSK Demodulator in the middle of each of the following 8 received data bits and stores the results in an
internal 8-bit shift register.
When the eighth data bit has been clocked into the internal shift register, the CMX602B examines the RXCLK
input. If RXCLK input is low, then the IRQ output will be pulled low, thereby sending the first of the stored
data bits to the RXD output pin. Upon detecting that the IRQ output has gone low, the C should pulse the
RXCLK pin high 8 times. The high to low transition at the end of the first 7 of these pulses will be used by the
CMX602B to shift the next data bit from the shift register onto the RXD output. At the end of the eighth pulse,
the FSK Demodulator output will be reconnected to the RXD output pin. The IRQ output will be cleared the
first time the RXCLK input goes high.
Thus to use the Data Retiming function, the RXCLK input should be kept low until the IRQ output goes low; if
the Data Retiming function is not required the RXCLK input should continuously be kept high.
The only restrictions on the timing of the RXCLK waveform are those shown in Figure 7 and the need to
complete the transfer of all eight bits into the C within 8.3ms (to empty the buffer before the next character is
received and put into the buffer).
2000 MX-COM, Inc
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Doc. # 20480204.002
4800 Bethania Station Road, Winston-Salem, NC 27105-1201, USA
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