CMX969D5 MX-COM, Inc., CMX969D5 Datasheet - Page 24

• Manufacturer Part Number: CMX969D5
• Description: MOTIENT/ARDIS RD-LAP MDC4800 Modem
• Manufacturer: MX-COM, Inc.

MOTIENT
4.6.4
The previous task timing figures are based on the signal at the input to the low pass filter (in transmit mode)
or the input to the de-interleave buffer (in receive mode). In RD-LAP mode there is an additional delay of
about 8 symbol times through to the RRC filter in both transmit and receive modes, as illustrated below: The
corresponding delay in MDC mode is about 3 symbol times.
4.6.5
This register may be read by the µC to determine the current state of the modem.
4.6.5.1
This bit is set to '1' by:
The IRQ bit is cleared to '0' immediately after a read of the Status Register.
If the
IRQ bit is set to '1', and will go high impedance when the Status Register is read.
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4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
or
or
or
IRQ
SM
Lowpass Filter Delay
Status Register
/ARDIS
Status Register B7: IRQ - Interrupt Request
EN
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a
change to the Mode Register
The Status Register IBEMPTY/AFSDET bit going from '0' to '1', unless this is caused by a RESET
task or by changing the Mode Register
The Status Register DIBOVF bit going from '0' to '1'.
The Status Register SRDY bit being set to '1' (due to a 'S' symbol or channel status bit being
received or transmitted) if the Mode Register SSIEN bit is '1'.
bit of the Mode Register is '1', then the chip IRQ output will be pulled low (to V
SM
RD-LAP
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TM
Figure 13: RRC Low Pass Filter Delay (RD-LAP mode)
MDC4800 Modem
Status Register
IRQ
Tx Symbol to RRC Filter
Tx Symbol at TXOUT pin / Rx Symbol from FM discriminator
Rx Symbol to De-interleave Buffer
Symbol-times
7
BFREE
6
TX/
IBEMPTY
/ AFSDET
RX
5
, ZP or PSAVE bits.
DIBOVF
TX/
4
RX
CRCERR
24
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, ZP or PSAVE bits.
3
SRDY
2
1
See text
0
CMX969 Advance Information
SS
Doc. # 20480211.002
) whenever the