CDS-1402 Datel, Inc., CDS-1402 Datasheet - Page 7
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CDS-1402
Manufacturer Part Number
CDS-1402
Description
Faster-settling Correlated Double Sampling Circuit: 14-bit
Manufacturer
Datel, Inc.
Datasheet
1.CDS-1402.pdf
(8 pages)
CALIBRATION PROCEDURE
Offset Adjust (Figure 5)
Offset and pedestal errors may be compensated for by
applying external voltages to pin 1 (OFFSET ADJUST V1) and/
or pin 9 (OFFSET ADJUST V2) using either voltage-output
DAC’s or potentiometers configured to appear as voltage
sources.
1. Connect pin 8 (S/H2 SUMMING NODE) either directly to pin
2. Tie pins 3 (ANALOG INPUT 1) and 4 (ANALOG INPUT 2) to
3. Adjust OFFSET ADJUST V1 (while S/H1 is in the hold
4. Adjust OFFSET ADJUST V2 (while S/H2 is in the hold
5. To negate the effect of output droop on the offset-adjust
7 (S/H1 ROUT) or through a 100 Ohm potentiometer to pin
6 (S/H1 OUT).
pin 5 (ANALOG GROUND).
mode) until pin 6 (S/H1 OUT) equals 0V.
mode) until pin 22 (V OUT) equals 0V.
process, each S/H must be continually switched between its
sample and hold modes and adjusted so its output equals
zero immediately after going into the hold mode.
®
100
®
+5V
–5V
+5V
–5V
10
11
12
Figure 5. CDS-1402 Typical Connection Diagram
2
3
4
5
6
7
8
9
1
S/H1 OUT
OFFSET ADJUST V1
ANALOG INPUT 1
ANALOG INPUT 2
ANALOG GROUND
OFFSET ADJUST V2
S/H1 COMMAND
S/H2 COMMAND
DO NOT CONNECT
S/H1 ROUT
S/H2 SUMMING NODE
DO NOT CONNECT
CDS-1402
7
The sensitivity of the voltage offset adjustments is 5mV per Volt.
Pins 1 and 9 should be left open (floating) when not being used
for offset adjustment.
Gain Matching Adjustment (Differential Gain)
between S/H1 and S/H2
The user can adjust the gain matching (differential gain)
between S/H1 and S/H2 by leaving pin 7 (S/H1 ROUT) floating
(open) and connecting a 100 Ohm potentiometer between pin
6 (S/H1 OUT) and pin 8 (S/H2 SUMMING NODE). Note, offset
adjustment should take place before gain matching adjustment.
Apply a full-scale input to both pin 3 (ANALOG INPUT 1) and
pin 4 (ANALOG INPUT 2). Adjust the 100 Ohm potentio-
meter (with both S/H's in the sample mode) until pin 22
(V OUT) is 0V.
If gain matching adjustment is not required, leave pin 6 (S/H1
OUT) floating (open) and tie pin 7 (S/H1 ROUT) to pin 8 (S/H2
SUMMING NODE).
+5V ANALOG SUPPLY
–5V ANALOG SUPPLY
+5V DIGITAL SUPPLY
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
DIGITAL GROUND
A/D CLOCK 1
A/D CLOCK 2
A/D CLOCK 2
A/D CLOCK 1
V OUT
18
24
23
19
22
21
20
17
16
15
14
13
0.1µF
0.1µF
0.1µF
+
+
+
2.2µF
2.2µF
2.2µF
+5V
–5V
+5V
CDS-1402