IDT82V2048 Integrated Device Technology, Inc., IDT82V2048 Datasheet - Page 5

• Manufacturer Part Number: IDT82V2048
• Manufacturer: Integrated Device Technology, Inc.

IDT82V2048 OCTAL T1/E1 SHORT HAUL LINE INTERFACE UNIT
PIN DESCRIPTION (CONTINUED)
BPVI0/TDN0
BPVI1/TDN1
BPVI2/TDN2
BPVI3/TDN3
BPVI4/TDN4
BPVI5/TDN5
BPVI6/TDN6
BPVI7/TDN7
TD0/TDP0
TD1/TDP1
TD2/TDP2
TD3/TDP3
TD4/TDP4
TD5/TDP5
TD6/TDP6
TD7/TDP7
TCLK0
TCLK1
TCLK2
TCLK3
TCLK4
TCLK5
TCLK6
TCLK7
Name
Type
I
I
QFP144 BGA160
108
101
109
102
144
107
100
37
30
80
73
38
31
79
72
36
29
81
74
8
1
7
9
2
Pin No.
N13
B13
D13
N12
B12
D12
N14
B14
D14
L13
L12
L14
N2
D2
N3
D3
N1
D1
B2
B3
B1
L2
L3
L1
TDn: Transmit Data for Channel 0~7
When the device is in Single Rail Mode, the NRZ data to be transmitted is input on this pin. Data on
TDn is sampled into the device on falling edges of TCLKn, and encoded by AMI or HDB3/B8ZS line
code rules before being transmitted to the line.
BPVIn: Bipolar Violation Insertion for Channel 0~7
Bipolar violation insertion is available in Single Rail Mode 2 (see table-1) with AMI enabled. A low-to-
high transition on this pin will make the next logic one to be transmitted on TDn the same polarity as the
previous pulse, and violate the AMI rule. This is for testing.
TDPn/TDNn: Positive/Negative Transmit Data for Channel 0~7
When the device is in Dual Rail Mode, the NRZ data to be transmitted for positive/negative pulse is input
on this pin. Data on TDPn/TDNn are active high and sampled on falling edge of TCLKn. The line code in
dual rail mode is as the follows :
Pulling pin TDNn high for more than 16 consecutive TCLK clock cycles will configure the corresponding
channel into single rail mode 1 (see table-1 on Page14).
TCLKn: Transmit Clock for Channel 0~7
The clock of 1.544 MHz (for T1 mode) or 2.048 MHz (for E1 mode) for transmit is input on this pin. The
transmit data at TDn/TDPn or TDNn is sampled into the device on falling edge of TCLKn.
Pulling TCLKn high for more than 16 MCLK cycles, the corresponding transmitter is set in Transmit All
One (TAO) state (when MCLK is clocked). In TAO state, the TAO generator adopts MCLK as the time
reference.
If TCLKn is Low, the corresponding transmit channel is set into power down state, while driver output
ports become high impedance.
Different combinations of TCLKn and MCLK result in different transmit mode. It is summarized as the
follows:
High/Low
High/Low
Clocked
Clocked
Clocked
MCLK
High ( 16 MCLK) Transmit All One (TAO) signals to the line side in the
Low ( 64 MCLK) Corresponding transmit channel is set into power down state.
TCLK1 is clocked
TCLK1 is not
(High/Low)
available
Clocked
TCLKn
TDPn
0
0
1
1
5
Normal operation
corresponding transmit channel.
TCLKn is clocked Normal operation
TCLKn is high
( 16 TCLK1)
TCLKn is low
( 64 TCLK1)
The receive path i s not affected by the status of TCLK1. When
MCLK is high, all receive paths just slice the incoming data stream.
When MCLK is low, all the receive paths are powered down.
All eight transmitters (TTIPn & TRINGn) will be in high impedance
state.
TDNn
0
1
0
1
Description
Space
Negative Pulse
Positive Pulse
Space
Transmit All One (TAO) signals to the line side
in the corresponding transmit channel.
Corresponding transmit channel is set into
power down state.
INDUSTRIAL TEMPERATURE RANGES
Output Pulse
Transmitter Mode