GS1503-CFZ Gennum Corp., GS1503-CFZ Datasheet - Page 23

• Manufacturer Part Number: GS1503-CFZ
• Description: HD EMBEDDED AUDIO CODEC
• Manufacturer: Gennum Corp.

1.6.3 Audio Clock Phase Locked Loop
Figure 22 shows the configuration for deriving the
6.144MHz audio clock in AES/EBU audio input mode. The
GS1503 will internally synchronize the AES/EBU audio input
to the corresponding ACLK, using the clock extracted from
the AES/EBU bi-phase mark encoding. This configuration is
not required for serial audio input modes. See the
Reference Design Section 3 for circuit specifics.
1.6.4 Audio Signal Input Detection
The audio input signal detect registers will be set HIGH in
AES/EBU audio mode when the preamble of the audio input
data is detected 3 times consecutively. In serial audio input
mode, the GS1503 will set the audio input signal detect
Register Settings
AUD7/8_DET
AUD5/6_DET
AUD3/4_DET
AUD1/2_DET
Y/C b / C r [19:0]
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
NAME
Ch7/8 Audio input signal detection (1:Detection)
Ch5/6 Audio input signal detection (1:Detection)
Ch3/4 Audio input signal detection (1:Detection)
Ch1/2 Audio input signal detection (1:Detection)
VIN[19:0]
AIN1/2
AIN3/4
ACLKA
AIN5/6
AIN7/8
ACLKB
DESCRIPTION
Fig. 22 Block Diagram of GS1503 Audio Clock PLL
GS1503
PLLCNTA
PLLCNTB
23 of 83
registers HIGH when a 48kHz word clock is detected at the
corresponding inputs. Audio channels 1 to 4 will be set
when WCINA is validated, and audio channels 5 to 8 when
WCINB is validated. Host Interface register 010h, bits 6-3,
report the individual audio channels pairs detected.
6.144MHz (128 fs)
6.144MHz (128 fs)
ADDRESS
Pass
Filter
Pass
Filter
Low
Low
010
24.576MHz
24.576MHz
BIT
6
5
4
3
VCXO
VCXO
SETTING
-
-
-
-
÷4
÷4
DEFAULT
15879 - 4
0
0
0
0