GS1503-CFZ Gennum Corp., GS1503-CFZ Datasheet - Page 58

• Manufacturer Part Number: GS1503-CFZ
• Description: HD EMBEDDED AUDIO CODEC
• Manufacturer: Gennum Corp.

2.10.2 Audio Group Designation Ancillary Data Deletion
When the ANCI bit 1 of Host Interface register 040h is set
HIGH, and DEL_SEL bit 0 of Host Interface register 040h is
HIGH, only audio data and control packets which are
designated in Host Interface registers 041h will be deleted.
To delete the arbitrary data packets, the corresponding DID
must be set in the NDID[7:0] Host Interface register 042h.
Register Settings
2.11 DEMULTIPLEX MODE WITH WORD CLOCK INPUT
Some
modules do not encode the audio word clock phase
information correctly in the CLK words of the audio data
packet. If this clock information is not correctly encoded,
the GS1503 will not output the audio data correctly. Also,
the GS1503 will be unable to reproduce the 48kHz audio
word clock (fs) at the WCOUTA and WCOUTB pins in serial
audio output modes.
If the GS1503 is to be used in conjunction with a HD audio
module, which encodes audio clock phase information
incorrectly, the DEC_MODE external pin or DECMODE bit 2
of Host Interface register 01Eh must be set HIGH. When
Register Settings
ADPG4_DEL
ADPG3_DEL
ADPG2_DEL
ADPG1_DEL
ACPG4_DEL
ACPG3_DEL
ACPG2_DEL
ACPG1_DEL
DECMODE
MUXERRB
MUXERRA
NDID[7:0]
DEL_SEL
NAME
NAME
commercially available HD audio embedding
ANCI
Ancillary data packet delete (1: Deletion enabled)
Ancillary data packet delete mode select
(0: Entire data delete; 1: Group designated data delete)
Audio group 4 data packet delete (1: Delete)
Audio group 3 data packet delete (1: Delete)
Audio group 2 data packet delete (1: Delete)
Audio group 1 data packet delete (1: Delete)
Audio group 4 control packet delete (1: Delete)
Audio group 3 control packet delete (1: Delete)
Audio group 2 control packet delete (1: Delete)
Audio group 1 control packet delete (1: Delete)
Arbitrary packet DID delete setting
Demultiplex Mode with word clock input enable
(1: Enabled)
Ch5-8 embedded clock phase information error detect
(1: Detected)
Ch1-4 embedded clock phase information error detect
(1: Detected)
DESCRIPTION
DESCRIPTION
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HIGH, an audio word clock synchronous to the original
word clock used for embedding must be input at the
WCINA and WCINB pins. Figure 43 shows a system
example.
When the embedded clock phase data for audio channel 1
to 4 is detected as being in error, the MUXERRA bit 0 of
Host Interface register 01Eh will be set HIGH. Similarly,
when the embedded clock phase data for audio channel 5
to 8 is detected as being in error, the MUXERRB bit 1 of
Host Interface register 01Eh will be set HIGH
ADDRESS
ADDRESS
01E
040
041
042
BIT
BIT
7-0
2
1
0
1
0
7
6
5
4
3
2
1
0
SETTING
SETTING
1
-
-
1
1
-
-
-
-
-
-
-
-
-
DEFAULT
DEFAULT
0
0
0
15879 - 4
0
0
0
0
0
0
0
0
0
0
0