MCP1726 Microchip Technology, MCP1726 Datasheet - Page 15

• Manufacturer Part Number: MCP1726
• Description: 1A Low Voltage / Low Quiescent Current LDO Regulator
• Manufacturer: Microchip Technology

4.4
Low input source impedance is necessary for the LDO
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
of 1.0 µF to 4.7 µF is recommended for most applica-
tions.
For
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from in order to respond quickly to
the output load step. For good step response perfor-
mance, the input capacitor should be of equivalent (or
higher) value than the output capacitor. The capacitor
should be placed as close to the input of the LDO as is
practical. Larger input capacitors will also help reduce
any high-frequency noise on the input and output of the
LDO and reduce the effects of any inductance that
exists between the input source voltage and the input
capacitance of the LDO.
4.5
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see the
Electrical Characteristics table for Min/Max specs) of its
nominal regulation value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
power good time delay is started (shown as T
Electrical Characteristics table). The power good time
delay is adjustable via the C
Section 4.6 “C
from the C
delay can be adjusted from 200 µs (no capacitance) to
300 ms (0.1 µF capacitor). After the time delay period,
the PWRGD output will go high, indicating that the out-
put voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 170 µs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
Figure 4-3.
© 2005 Microchip Technology Inc.
applications
Input Capacitor
Power Good Output (PWRGD)
DELAY
DELAY
pin to ground, the power good time
that
Input”). By placing a capacitor
have
DELAY
output
pin of the LDO (see
step
PG
in the
load
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA (V
FIGURE 4-2:
FIGURE 4-3:
Shutdown.
4.6
The C
delay timing for the power good output, as discussed in
the previous section. By adding a capacitor from the
C
delay can be adjusted from 200 µs (no capacitance on
C
See the Electrical Characteristics table for C
timing tolerances.
DELAY
DELAY
V
PWRGD
V
V
SHDN
IN
OUT
PWRGD_TH
V
30 ms
PWRGD
OUT
DELAY
) to 300 ms (0.1 µF of capacitance on C
pin to ground, the PWRGD power-up time
C
PWRGD
DELAY
input is used to provide the power-up
T
OR
70 ms
T
< 0.4V maximum).
PG
Input
Power Good Timing.
Power Good Timing from
V
OH
T
PG
MCP1726
DS21936B-page 15
T
VDET_PWRGD
V
OL
DELAY
DELAY
).