ACS112MS Intersil Corporation, ACS112MS Datasheet
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ACS112MS
Manufacturer Part Number
ACS112MS
Description
Radiation Hardened Dual J-k Flip-flop
Manufacturer
Intersil Corporation
Datasheet
1.ACS112MS.pdf
(3 pages)
January 1996
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
• Dose Rate Upset . . . . . . . . . . . . . . . . >10
• Dose Rate Survivability . . . . . . . . . . . >10
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
• Input Current ≤ 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 21ns (Max), 14ns (Typ)
Description
The Intersil ACS112MS is a Radiation Hardened Dual J-K Flip-Flop with
Set and Reset. The output change states on the negative transition of
the clock (CP1N or CP2N).
The ACS112MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of the radiation hard-
ened, high-speed, CMOS/SOS Logic Family.
The ACS112MS is supplied in a 16 lead Ceramic Flatpack (K suffix) or a
Ceramic Dual-In-Line Package (D suffix).
Ordering Information
5962F9670401VEC
5962F9670401VXC
ACS112D/Sample
ACS112K/Sample
ACS112HMSR
SMD# 5962-96704 and Intersil’sIntersil QM Plan
(Typ)
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
PART NUMBER
|
TM
Intersil (and design) is a trademark of Intersil Americas Inc.
TEMPERATURE RANGE
-55
-55
o
o
C to +125
C to +125
25
25
25
o
o
o
C
C
C
11
12
o
o
C
C
RAD (Si)/s, 20ns Pulse
RAD (Si)/s, 20ns Pulse
-10
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
Errors/Bit/Day
o
C to +125
1
SCREENING LEVEL
2
/mg
o
C
ACS112MS
Pinouts
GND
CP1
MIL-STD-1835, DESIGNATOR CDFP4-F16,
K1
Q1
Q1
Q2
MIL-STD-1835, DESIGNATOR CDIP2-T16,
S1
J1
16 PIN CERAMIC DUAL-IN-LINE
GND
16 PIN CERAMIC FLATPACK
CP1
Q1
Q1
Q2
K1
S1
J1
1
2
3
4
5
6
7
8
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
LEAD FINISH C
LEAD FINISH C
1
2
3
4
5
6
7
8
Radiation Hardened
TOP VIEW
TOP VIEW
Dual J-K Flip-Flop
Spec Number
PACKAGE
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
VCC
R1
R2
CP2
K2
J2
S2
Q2
FN3571.1
518816
VCC
R1
R2
CP2
K2
J2
S2
Q2