LM185BYH-2.5 National Semiconductor, LM185BYH-2.5 Datasheet - Page 3

• Manufacturer Part Number: LM185BYH-2.5
• Description: Micropower Voltage Reference Diode
• Manufacturer: National Semiconductor

Register Description
Bits 0–2
Bits 3–4
Double Equalization and Serration mode will output equal-
ization and serration pulses at twice the HSYNC frequency
(i.e., 2 equalization or serration pulses for every HSYNC
pulse). Single Equalization and Serration mode will output
an equalization or serration pulse for every HSYNC pulse. In
Interlaced mode equalization and serration pulses will be
output during the VBLANK period of every odd and even
field. Interlaced Single Equalization and Serration mode is
not possible with this part.
Bits 5–8
Bits 5 through 8 control the polarity of the outputs. A value of
zero in these bit locations indicates an output pulse active
LOW. A value of 1 indicates an active HIGH pulse.
B5 —
B6 —
B7 —
B8 —
Bits 9–11
Bits 9 through 11 enable several different features of the de-
vice.
B9 —
B10 —
B11 —
(DEFAULT)
(DEFAULT)
B
B
0
0
0
0
1
1
1
1
0
0
1
1
2
4
B
0
0
1
1
0
0
1
1
1
VCBLANK Polarity
VCSYNC Polarity
HBLHDR Polarity
HSYNVDR Polarity
B
Enable Equalization/Serration Pulses (0)
Disable Equalization/Serration Pulses (1)
Disable System Clock (0)
Enable System Clock (1)
Default values for B10 are “0” in the ’ACT715/
LM1882 and “1” in the ’ACT715-R/LM1882-R.
Disable Counter Test Mode (0)
Enable Counter Test Mode (1)
This bit is not intended for the user but is for internal
testing only.
0
1
0
1
3
B
0
1
0
1
0
1
0
1
0
Interlaced Double Serration and
Equalization
Non Interlaced Double Serration
Illegal State
Non Interlaced Single Serration and
Equalization
VCBLANK
CBLANK
CBLANK
CBLANK
CBLANK
VBLANK
VBLANK
VBLANK
VBLANK
Mode of Operation
VCSYNC
CSYNC
CSYNC
VSYNC
VSYNC
CSYNC
CSYNC
VSYNC
VSYNC
(Continued)
CURSOR
CURSOR
HBLHDR HSYNVDR
HBLANK
HBLANK
HBLANK
HBLANK
HGATE
HGATE
VGATE
VGATE
HSYNC
HSYNC
HSYNC
HSYNC
VINT
VINT
3
HORIZONTAL INTERVAL REGISTERS
The Horizontal Interval Registers determine the number of
clock cycles per line and the characteristics of the Horizontal
Sync and Blank pulses.
REG1 —
REG2 —
REG3 —
REG4 —
VERTICAL INTERVAL REGISTERS
The Vertical Interval Registers determine the number of lines
per frame, and the characteristics of the Vertical Blank and
Sync Pulses.
REG5 —
REG6 —
REG7 —
REG8 —
EQUALIZATION AND SERRATION PULSE
SPECIFICATION REGISTERS
These registers determine the width of equalization and ser-
ration pulses and the vertical interval over which they occur.
REG 9 —
REG10 — Serration Pulse Width End Time
REG11 — Equalization/Serration Pulse Vertical
REG12 — Equalization/Serration Pulse Vertical
VERTICAL INTERRUPT SPECIFICATION REGISTERS
These Registers determine the width of the Vertical Interrupt
signal if used.
REG13 —
REG14 —
CURSOR LOCATION REGISTERS
These 4 registers determine the cursor position location, or
they generate separate Horizontal and Vertical Gating sig-
nals.
REG15 —
REG16 —
REG17 —
REG18 —
Signal Specification
HORIZONTAL SYNC AND BLANK
SPECIFICATIONS
All horizontal signals are defined by a start and end time.
The start and end times are specified in number of clock
cycles per line. The start of the horizontal line is considered
pulse 1 not 0. All values of the horizontal timing registers are
referenced to the falling edge of the Horizontal Blank signal
(see Figure 1 ). Since the first CLOCK edge, CLOCK # 1,
causes the first falling edge of the Horizontal Blank reference
pulse, edges referenced to this first Horizontal edge are n +
1 CLOCKs away, where “n” is the width of the timing in ques-
tion. Registers 1, 2, and 3 are programmed in this manner.
The horizontal counters start at 1 and count until HMAX. The
value of HMAX must be divisible by 2. This limitation is im-
Horizontal Front Porch
Horizontal Sync Pulse End Time
Horizontal Blanking Width
Horizontal Interval Width
Line
Vertical Front Porch
Vertical Sync Pulse End Time
Vertical Blanking Width
Vertical Interval Width
Equalization Pulse Width End Time
Interval Start Time
Interval End Time
Vertical Interrupt Activate Time
Vertical Interrupt Deactivate Time
Horizontal Cursor Position Start Time
Horizontal Cursor Position End Time
Vertical Cursor Position Start Time
Vertical Cursor Position End Time
# of Lines per Frame
# of Clocks per
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