LM185BYH-2.5 National Semiconductor, LM185BYH-2.5 Datasheet - Page 4

• Manufacturer Part Number: LM185BYH-2.5
• Description: Micropower Voltage Reference Diode
• Manufacturer: National Semiconductor

www.national.com
Signal Specification
posed because during interlace operation this value is inter-
nally divided by 2 in order to generate serration and equal-
Horizontal Period (HPER)
Horizontal Blanking Width:
Horizontal Sync Width:
Horizontal Front Porch:
VERTICAL SYNC AND BLANK SPECIFICATION
All vertical signals are defined in terms of number of lines per
frame. This is true in both interlaced and noninterlaced
modes of operation. Care must be taken to not specify the
Vertical Registers in terms of lines per field. Since the first
CLOCK edge, CLOCK # 1, causes the first falling edge of the
Vertical Blank (first Horizontal Blank) reference pulse, edges
referenced to this first edge are n + 1 lines away, where “n”
is the width of the timing in question. Registers 5, 6, and 7
are programmed in this manner. Also, in the interlaced
mode, vertical timing is based on half-lines. Therefore regis-
ters 5, 6, and 7 must contain a value twice the total horizontal
(odd and even) plus 1 (as described above). In
non-interlaced mode, all vertical timing is based on
whole-lines. Register 8 is always based on whole-lines and
does not add 1 for the first clock. The vertical counter starts
at the value of 1 and counts until the value of VMAX. No re-
strictions exist on the values placed in the vertical registers.
Vertical Blank will change on the leading edge of HBLANK.
Vertical Sync will change on the leading edge of HSYNC.
(See Figure 2 .)
Vertical Frame Period (VPER) = REG(8) x hper
Vertical Field Period (VPER/n) = REG(8) x hper/n
Vertical Blanking Width = [REG(7) − 1] x hper/n
=
=
=
= [REG(3) − 1] x ckper
REG(4) x ckper
[REG(2) − REG(1)] x ckper
[REG(1) − 1] x ckper
(Continued)
FIGURE 1. Horizontal Waveform Specification
4
ization pulses at 2 x the horizontal frequency. Horizontal
signals will change on the falling edge of the CLOCK signal.
Signal specifications are shown below.
Vertical Syncing Width = [REG(6) − REG(5)] x hper/n
Vertical Front Porch = [REG(5) − 1] x hper/n
where
COMPOSITE SYNC AND BLANK SPECIFICATION
Composite Sync and Blank signals are created by logically
ANDing (ORing) the active LOW (HIGH) signals of the corre-
sponding vertical and horizontal components of these sig-
nals. The Composite Sync signal may also include serration
and/or equalization pulses. The Serration pulse interval oc-
curs in place of the Vertical Sync interval. Equalization
pulses occur preceding and/or following the Serration
pulses. The width and location of these pulses can be pro-
grammed through the registers shown below. (See Figure 3 .)
Horizontal Equalization PW = [REG(9) − REG(1)] x ckper
Horizontal Serration PW:
Where
n = 1 for noninterlaced
n = 2 for interlaced
n
equalization
n
equalization
n = 2 for interlaced operation
=
=
2
1
for
for
noninterlaced
noninterlaced
=
REG 9 = (HFP) + (HEQP) + 1
[REG(4)/n
REG(10)] x ckper
REG
(HPER/2) − (HSERR) + 1
DS100232-4
10
double
single
+
=
REG(1)
(HFP)
serration/
serration/
−
+