Si9118 Vishay Intertechnology, Si9118 Datasheet - Page 8

• Manufacturer Part Number: Si9118
• Manufacturer: Vishay Intertechnology

Si9118/Si9119
Vishay Siliconix
The maximum duty cycle limitation will be different when the
converter is synchronized by an external frequency. If the
internal free running frequency is much slower than the
external SYNC signal (SYNC signal causes the internal clock
to reset before the Cosc voltage ramps to 3.2 V) , duty cycle is
determined by the one shot discharge time of the oscillator
capacitor (100 ns). Therefore, with 1-MHz SYNC signal,
maximum duty cycle of 90% can be achieved (100 ns is 10%
of 1 MHz). If the internal free running frequency is very close
to the external SYNC frequency (SYNC signal causes the
internal clock to reset somewhere between 3.2 V to 4 V), duty
cycle is determined by the ratio of C
point and the 3.2 V. At this condition, the maximum duty cycle
can be greater than 90%. Therefore, D
modified in order to maintain desired maximum duty cycle.
Slope Compensation
Slope compensation is necessary for duty cycles greater than
50% to stabilize the inner current loop and maintain overall
loop stability. In order to simplify the slope compensation
circuitry, the Si9118 provides the buffered oscillator ramp
signal, V
is only available when DR is high. The V
super-imposed with actual current sense signal should be
used by the PWM comparator to determine the duty cycle. The
summation of this signal should be fed into I
optimum performance, proper slope compensation is
required. The amount of slope compensation is determined by
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8
SC
to be used for external slope compensation. V
osc
voltage at the SYNC
MAX
voltage must be
CS
SC
pin. For
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signal
SC
the resistors connected to the I
V
designs which use with SYNC pin, instead of V
converter can still operate at duty cycles greater than 50% by
generating an external slope compensation ramp using a
simple RC circuit from the MOSFET driver output pin as shown
on the application circuit.
Over Current Protection
Si9118/Si9119 are designed with a pulse-to-pulse peak
current limiting protection circuit to protect itself, and the load
in case of a failure. The voltage across the sense resistor is
monitored continuously and if the voltage reaches its trigger
level, the duty cycle is terminated. This limits the maximum
current delivered to the load. In order to improve the accuracy
of over current protection from traditional controllers,
Si9118/Si9119 are designed with separate I
Voltage on the I
compensation voltage, which adds error into the detection
level. I
slope compensation for loop stability.
Output Driver Stage
The DR pin is designed to drive a low-side n-channel
MOSFET. The driver stage is sized to sink and source peak
currents up to 500 mA with V
drive capability for 50 W of output power.
SC
signal is same as the C
CS
pin is used to sum the current sense signal and the
LIMIT
pin does not sum in the traditional slope
CC
OSC
CS
= 12 V. This provides ample
pin. The amplitude of the
pin voltage ( 4 V). For
S-60752—Rev. B, 05 Apr-99
Document Number: 70815
LIMIT
and I
SC
pin, the
CS
pins.