AD9851 Analog Devices, AD9851 Datasheet - Page 20

• Manufacturer Part Number: AD9851
• Description: CMOS 180 MHz DDS/DAC Synthesizer
• Manufacturer: Analog Devices

AD9851
Figure 29. Narrowband (1.1
1.1 MHz fundamental output signal. System clock =
180 MHz (6 REFCLK Multiplier engaged), V
Figure 30. Narrowband (40.1
a 40.1 MHz fundamental output signal. System clock =
180 MHz (6 REFCLK Multiplier engaged), V
Figure 31. Narrowband (70.1
a 70.1 MHz fundamental output signal. System clock =
180 MHz (6 REFCLK Multiplier engaged), V
–100
–100
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
–10
–20
–30
–40
–50
–60
–70
–80
–90
CENTER
40.1MHz
CENTER
70.1MHz
CENTER
1.1MHz
0
0
0
20kHz/
20kHz/
20kHz/
0.1 MHz) output SFDR for a
0.1 MHz) output SFDR for
0.1 MHz) output SFDR for
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
S
S
S
= +5 V.
= +5 V.
= +5 V.
200kHz
200kHz
200kHz
SPAN
SPAN
SPAN
2AP
2AP
2AP
–20–
Figure 32. Typical CMOS comparator p-p output jitter
with the AD9851 configured as a clock generator, DDS f
= 10.1 MHz, V
LPF. Graph details the center portion of a rising edge with
scope in delayed trigger mode, 200 ps/div. Cursors show
208 ps p-p jitter.
Figure 33. Typical CMOS comparator p-p output jitter
with the AD9851 configured as a clock generator, DDS f
= 40.1 MHz, V
LPF. Graph details the center portion of a rising edge with
scope in delayed trigger mode, 200 ps/div. Cursors show
204 ps p-p jitter.
1
1
Tek Run 4.00GS/s
Tek Run 4.00GS/s
Ch1 200mV
Ch1 200mV
@ : 3.672ns
@ : 1.940ns
: 204ps
: 208ps
S
S
= +5 V, system clock = 180 MHz, 70 MHz
= +5 V, system clock = 180 MHz, 70 MHz
T
Sample
Sample
T
[
[
]
]
M 12.5ns Ch 1
D 200ps Runs After
M 12.5ns Ch 1
D 200ps Runs After
–200mV
–200mV
REV. C
OUT
OUT