AD9851 Analog Devices, AD9851 Datasheet - Page 8

• Manufacturer Part Number: AD9851
• Description: CMOS 180 MHz DDS/DAC Synthesizer
• Manufacturer: Analog Devices

AD9851
THEORY OF OPERATION AND APPLICATION
The AD9851 uses direct digital synthesis (DDS) technology, in
the form of a numerically-controlled oscillator (NCO), to gen-
erate a frequency/phase-agile sine wave. The digital sine wave is
converted to analog form via an internal 10-bit high speed D/A
converter. An on-board high-speed comparator is provided to
translate the analog sine wave into a low-jitter TTL/CMOS-
compatible output square wave. DDS technology is an innova-
tive circuit architecture that allows fast and precise manipulation
of its output word, under full digital control. DDS also enables
very high resolution in the incremental selection of output fre-
quency. The AD9851 allows an output frequency resolution of
approximately 0.04 Hz at 180 MSPS clock rate with the option of
directly using the reference clock or by engaging the 6 REFCLK
Multiplier. The AD9851’s output waveform is phase-continu-
ous from one output frequency change to another.
The basic functional block diagram and signal flow of the
AD9851 configured as a clock generator is shown in Figure 11.
The DDS circuitry is basically a digital frequency divider func-
tion whose incremental resolution is determined by the frequency
of the system clock, and N (number of bits in the tuning word).
The phase accumulator is a variable-modulus counter that
increments the number stored in it each time it receives a clock
pulse. When the counter reaches full scale it “wraps around,”
making the phase accumulator’s output phase-continuous. The
frequency tuning word sets the modulus of the counter, which
effectively determines the size of the increment ( Phase) that
will be added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the
accumulator wraps around, which results in a higher output
frequency.
The AD9851 uses an innovative and proprietary “Angle
Rotation” algorithm that mathematically converts the 14-bit
truncated value of the 32-bit phase accumulator to the 10-bit
quantized amplitude that is passed to the DAC. This unique
TUNING WORD SPECIFIES
OUTPUT FREQUENCY AS A
FRACTION OF REF CLOCK
FREQUENCY
N
(DC)
0Hz
Figure 11. Basic DDS Block Diagram and Signal Flow of AD9851
ACCUMULATOR
REFERENCE
20MHz
F
OUT
Figure 12. Output Spectrum of a Sampled Sin(X)/X Signal
CLOCK
PHASE
SYSTEM CLOCK FREQUENCY
1ST IMAGE
DDS CIRCUITRY
80MHz
SIN (X)/
F
C
= ( )F/F
–F
CONV ALGORITHM
AMPLITUDE/SINE
O
100MHz
F
C
ENVELOPE
IN DIGITAL
C
DOMAIN
2ND IMAGE
F
120MHz
C
+F
O
–8–
3RD IMAGE
180MHz
CONVERTER
2F
algorithm uses a much-reduced ROM look-up table and DSP to
perform this function. This contributes to the small size and
low power dissipation of the AD9851.
The relationship between the output frequency, system clock
and tuning word of the AD9851 is determined by the expression:
where:
System Clock = direct input reference clock (in MHz) or 6 the
input clock (in MHz) if the 6 REFCLK Multiplier is engaged.
f
The digital sine wave output of the DDS core drives the internal
high-speed 10-bit D/A converter that will construct the sine
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy, which results in the low
spurious and jitter performance of the AD9851. The DAC can
be operated in either the single-ended, Figures 2 and 8, or dif-
ferential output configuration, Figures 9 and 10. DAC output
current and R
expressions:
Since the output of the AD9851 is a sampled signal, its output
spectrum follows the Nyquist sampling theorem. Specifically, its
output spectrum contains the fundamental plus aliased signals
(images) that occur at integer multiples of the system clock
frequency
sentation of the sampled spectrum, with aliased images, is shown in
Figure 12. Normal usable bandwidth is considered to extend
from dc to 1/2 the system clock.
In the example shown in Figure 12, the system clock is 100 MHz
and the output frequency is set to 20 MHz. As can be seen, the
aliased images are very prominent and of a relatively high energy
OUT
Phase = decimal value of 32-bit frequency tuning word.
C
–F
D/A
O
= frequency of the output signal in MHz.
4TH IMAGE
2F
220MHz
C
the selected output frequency. A graphical repre-
+F
LP
SET
O
f
OUT
values are determined using the following
= ( Phase
COMPARATOR
5TH IMAGE
3F
280MHz
I
R
C
OUT
–F
SET
O
= 39.93/R
= 39.93/I
System Clock)/2
CLOCK
OUT
OUT
SET
32
REV. C