AD9995 Analog Devices, AD9995 Datasheet - Page 15

• Manufacturer Part Number: AD9995
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: Analog Devices

HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 13 shows an example CCD layout. The horizontal register
contains 28 dummy pixels, which will occur on each line clocked
from the CCD. In the vertical direction, there are 10 optical
black (OB) lines at the front of the readout and two at the back
of the readout. The horizontal direction has four OB pixels in the
front and 48 in the back.
Figure 14 shows the basic sequence layout to be used during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the noneffective CCD
pixels. HBLK is used during the vertical shift interval.
REV. 0
CLPOB
CCDIN
H1/H3
HBLK
PBLK
H2/H
SHP
SHD
HD
OPTICAL BLACK
VERTICAL SHIFT
28 DUMMY PIXELS
4 OB PIXELS
V
Figure 14. Horizontal Sequence Example
Figure 13. Example CCD Configuration
DUMMY
EFFECTIVE IMAGE AREA
HORIZONTAL CCD REGISTER
OB
H
–15–
EFFECTIVE PIXELS
The HBLK, CLPOB, and PBLK parameters are programmed in
the V-sequence registers.
More elaborate clamping schemes may be used, such as adding
in a separate sequence to clamp during the entire shield OB lines.
This requires configuring a separate V-sequence for reading out
the OB lines.
48 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
OPTICAL BLACK
AD9995
VERT SHIFT