AD9995 Analog Devices, AD9995 Datasheet - Page 5

• Manufacturer Part Number: AD9995
• Description: 12-Bit CCD Signal Processor with Precision Timing Generator
• Manufacturer: Analog Devices

TIMING SPECIFICATIONS
Parameter
MASTER CLOCK, CLI (Figure 4)
AFE CLPOB Pulsewidth
AFE SAMPLE LOCATION
DATA OUTPUTS (Figures 8a and 8b)
SERIAL INTERFACE (Figures 40a and 40b)
NOTES
1
2
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
TCVDD
HVDD
RGVDD
DVDD
DRVDD
RG Output
H1–H4 Output
Digital Outputs
Digital Inputs
SCK, SL, SDATA
REFT, REFB, CCDIN
Junction Temperature
Lead Temperature, 10 sec
*Stresses above those listed under Absolute Maximum Ratings may cause permanent
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9995 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. 0
Parameter is programmable.
Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance.
damage to the device. This is a stress rating only. Functional operation of the device
at these or any other conditions above those listed in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. Absolute maximum ratings apply
individually only, not in combination. Unless otherwise specified, all other voltages
are referenced to GND.
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI Rising Edge to Internal Pixel Position 0
SHP Sample Edge to SHD Sample Edge
Output Delay from DCLK Rising Edge
Pipeline Delay from SHP/SHD Sampling to DOUT
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
1, 2
With
Respect
To
AVSS
TCVSS
HVSS
RGVSS
DVSS
DRVSS
RGVSS
HVSS
DVSS
DVSS
DVSS
AVSS
(Figures 9 and 14)
1
(Figure 7)
Min
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
(C
L
1
= 20 pF, AVDD = DVDD = DRVDD = 3.0 V, f
Max
+3.9
+3.9
+3.9
+3.9
+3.9
+3.9
RGVDD + 0.3 V
HVDD + 0.3 V
DVDD + 0.3 V
DVDD + 0.3 V
DVDD + 0.3 V
AVDD + 0.3
150
350
Unit
V
V
V
V
V
V
V
°C
°C
–5–
Symbol
t
t
t
t
f
f
f
t
t
t
t
t
CONV
CLIDLY
S1
OD
SCLK
SCLK
LS
LH
DS
DH
DV
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance

*
Model
AD9995KCP
AD9995KCPRL
board.
JA
JA
= 25°C/W*
is measured using a 4-layer PCB with the exposed paddle soldered to the
CLI
= 36 MHz, unless otherwise noted.)
Min
27.8
11.2
2
12.5
10
10
10
10
10
10
Temperature
Range
–20°C to +85°C
–20°C to +85°C
ORDERING GUIDE
Typ
13.9
6
20
13.9
8
11
Package
Description
LFCSP
LFCSP
Max
16.6
AD9995
Package
Option
CP-56
CP-56
Unit
ns
ns
ns
Pixels
ns
ns
Cycles
MHz
ns
ns
ns
ns
ns