AD9510 Analog Devices, AD9510 Datasheet

AD9510

Manufacturer Part Number

AD9510

Description

Manufacturer

Analog Devices

Datasheet

1.AD9510.pdf (41 pages)

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Preliminary Technical Data

FEATURES

Low phase noise phase-locked loop core

Two 1.5 GHz, differential clock inputs

8 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

4 independent 800 MHz LVPECL outputs

4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

4-wire or 3-wire serial control port

Space-saving 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

GENERAL DESCRIPTION

The AD9510 provides a multi-output clock distribution

function along with an on-chip PLL core. The design

emphasizes low jitter and phase noise in order to maximize data

converter performance. Other applications with demanding

phase noise and jitter requirements also benefit from this part.

The PLL section consists of a programmable reference divider

(R); a low noise phase frequency detector (PFD); a precision

charge pump (CP); and a programmable feedback divider (N).

By connecting an external VCXO or VCO to the CLK2/CLK2B

pins, frequencies up to 1.5 GHz may be synchronized to the

input reference.

There are eight independent clock outputs. Four outputs are

LVPECL, and four are selectable as either LVDS or CMOS

levels. The LVPECL and LVDS outputs operate to 800 MHz, and

the CMOS outputs operate to 250 MHz.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

Reference input frequencies to 250 MHz

Programmable dual-modulus prescaler

Programmable charge pump (CP) current

Separate CP supply (VCP) extends tuning range

Additive output jitter 225 fs rms

Additive output jitter 275 fs rms

Fine delay adjust on 2 outputs, 6-bit delay words

800 MHz Clock Distribution IC, PLL Core,

Dividers, Delay Adjust, Eight Outputs

Each output has a programmable divider that may be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output may be varied by means

of a divider phase select function that serves as a coarse timing

adjustment. Two of the LVDS/CMOS outputs also feature

programmable delay elements with a range of up to 10 ns of

delay. This fine tuning delay block has 6-bit resolution, giving 64

possible delays from which to choose.

The AD9510 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9510 is available in a 64-lead LFCSP and may be

operated from a single 3.3 V supply. An external VCO which

requires an extended voltage range may be accommodated by

connecting the charge pump supply (VCP) to 5.5 V. The

temperature range is −40°C to +85°C.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

FUNCTION

REFINB

REFIN

CLK1B

SCLK

CLK1

SDIO

SDO

CSB

FUNCTIONAL BLOCK DIAGRAM

CONT ROL

RESETB PDB

SERIAL

PO RT

SYNCB ,

GND

DISTRIBUTION

PROGRAMMABLE DIVIDERS

RSET

REF

/1,/2,/3 ... /31,/32

& PHASE ADJUST

R DIVIDER

N DIVIDER

Figure 1.

AD9510

FREQUENCY

DETECTOR

PHASE

∆T

CPRSET

PLL

REF

SETTINGS

CHARGE

PUMP

PLL

www.analog.com

LVPECL

LVDS/CMOS

AD9510

VCP

STATUS

CLK2B

OUT0

OUT0B

OUT1

OUT1B

OUT2

OUT2B

OUT3

OUT3B

OUT4

OUT4B

OUT5

OUT5B

OUT6B

OUT7

OUT7B

OUT6

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